Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to process inputs, the processing circuitry comprising a plurality of sequential stages; clocked input circuitry to receive a flow of clocked inputs and provide said clocked inputs to the processing circuitry, said clocked inputs being synchronised with one or more clock signal of the processing circuitry; and asynchronous input circuitry to receive an asynchronous input and provide said asynchronous input to the processing circuitry. The asynchronous input is a deactivation signal to direct the processing circuitry to cease processing clocked inputs. Clock circuitry provides said one or more clock signals, said clock circuitry being responsive to said deactivation signal to control a deactivation of the one or more clock signals such that each of said plurality of sequential stages undergoes a respective corresponding number of clock cycles.