Abstract: Disclosed are techniques for reducing voltage drooping in a microelectronic chip, including separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, where the scan data launch clock and the capture clock are based on a base clock signal. The techniques further include analyzing and categorizing the latches against the time delay into dedicated buffer group categories. The techniques further include assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.

Abstract: Disclosed are techniques for reducing voltage drooping in a microelectronic chip, including separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, where the scan data launch clock and the capture clock are based on a base clock signal. The techniques further include analyzing and categorizing the latches against the time delay into dedicated buffer group categories. The techniques further include assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.