Abstract: A battery management system comprising: a synchronisation element comprising an oscillator wherein the synchronisation element is configured to generate a reference clock signal based on an output of the oscillator; and a plurality of measurement devices wherein each measurement device is configured to measure an electrical property of one or more battery cells and comprises a local oscillator configured to generate an individual clock signal; and wherein the plurality of measurement devices are connected in a communication network with the synchronisation element, and wherein: the synchronisation element is configured to send, by the communication network, time reference signals to the plurality of measurement devices based on the reference clock signal; each measurement device is configured to compare each time reference signal to its individual clock signal and, based on any detected difference, adjust its local oscillator to synchronize the individual clock signal with the reference clock signal.

Abstract: A sigma-delta ADC comprising: a first-input-resistor connected in series between a first-input-terminal and a first-feedback-node; a second-input-resistor connected in series between a second-input-terminal and a second-feedback-node; a third-input-resistor connected in series between a third-input-terminal and a third-feedback-node; a first-multiplexer-switch connected in series between the first-feedback-node and a first-amplifier-second-input-terminal; a second-multiplexer-switch connected in series between the second-feedback-node and a first-amplifier-first-input-terminal; a third-multiplexer-switch connected in series between the third-feedback-node and the first-amplifier-second-input-terminal; a first-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to a reference-terminal; a second-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal; a first-feedback-selecti

Abstract: A sigma-delta ADC comprising: a first-input-resistor connected in series between a first-input-terminal and a first-feedback-node; a second-input-resistor connected in series between a second-input-terminal and a second-feedback-node; a third-input-resistor connected in series between a third-input-terminal and a third-feedback-node; a first-multiplexer-switch connected in series between the first-feedback-node and a first-amplifier-second-input-terminal; a second-multiplexer-switch connected in series between the second-feedback-node and a first-amplifier-first-input-terminal; a third-multiplexer-switch connected in series between the third-feedback-node and the first-amplifier-second-input-terminal; a first-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to a reference-terminal; a second-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal; a first-feedback-selecti

Abstract: In a particular example, a low drift voltage reference system includes a Zener diode circuit, a voltage reduction circuit, and a proportional-to-absolute temperature (PTAT) circuit. The Zener diode circuit, which is coupled between a first supply terminal (e.g., VDD) and a second supply terminal (e.g., common), provides an input reference voltage level. The voltage reduction circuit provides another reduced version of the input reference voltage level. The PTAT circuit has first and second differential paths to provide an output reference voltage at an output node of the PTAT circuit, and a feedback path to draw feedback current from the output node to control the differential circuit.

Abstract: A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal; a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal; an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal. The sigma-delta ADC also includes a feedback-current-block, which comprises: a first-feedback-transistor having a conduction channel; a second-feedback-transistor having a conduction channel; a first-feedback-switch; a second-feedback-switch; a first-feedback-current-source; and a second-feedback-current-source.

Abstract: A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal; a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal; an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal. The sigma-delta ADC also includes a feedback-current-block, which comprises: a first-feedback-transistor having a conduction channel; a second-feedback-transistor having a conduction channel; a first-feedback-switch; a second-feedback-switch; a first-feedback-current-source; and a second-feedback-current-source.

Abstract: In a particular example, a low drift voltage reference system includes a Zener diode circuit, a voltage reduction circuit, and a proportional-to-absolute temperature (PTAT) circuit. The Zener diode circuit, which is coupled between a first supply terminal (e.g., VDD) and a second supply terminal (e.g., common), provides an input reference voltage level. The voltage reduction circuit provides another reduced version of the input reference voltage level. The PTAT circuit has first and second differential paths to provide an output reference voltage at an output node of the PTAT circuit, and a feedback path to draw feedback current from the output node to control the differential circuit.

Abstract: An integrated circuit includes a voltage reference circuit including a Zener diode having a first terminal coupled to a first node and a second terminal coupled to a first voltage supply terminal. A proportional to absolute temperature (PTAT) circuit is coupled at the first node and configured to generate a PTAT current. A PTAT compensation circuit is coupled at the first node. The PTAT compensation circuit includes a first current mirror having a first branch coupled at the first node.

Abstract: An apparatus, a method, and an integrated circuit for a providing a temperature-compensated Zener reference are disclosed. In accordance with at least one embodiment, the apparatus comprises a proportional-to-absolute-temperature (PTAT) current source; a complementary-to-absolute-temperature (CTAT) current source; and a Zener diode, with the PTAT current source coupled to a first Zener diode terminal of the Zener diode, the CTAT current source coupled to the first Zener diode terminal of the Zener diode, and the PTAT current source providing a PTAT current and the CTAT current source providing a CTAT current, wherein the PTAT current and the CTAT current are combined for provide a temperature-compensated bias current.

Abstract: An apparatus, a method, and an integrated circuit for a providing a temperature-compensated Zener reference are disclosed. In accordance with at least one embodiment, the apparatus comprises a proportional-to-absolute-temperature (PTAT) current source; a complementary-to-absolute-temperature (CTAT) current source; and a Zener diode, with the PTAT current source coupled to a first Zener diode terminal of the Zener diode, the CTAT current source coupled to the first Zener diode terminal of the Zener diode, and the PTAT current source providing a PTAT current and the CTAT current source providing a CTAT current, wherein the PTAT current and the CTAT current are combined for provide a temperature-compensated bias current.

Abstract: An integrated circuit includes a voltage reference circuit including a Zener diode having a first terminal coupled to a first node and a second terminal coupled to a first voltage supply terminal. A proportional to absolute temperature (PTAT) circuit is coupled at the first node and configured to generate a PTAT current. A PTAT compensation circuit is coupled at the first node. The PTAT compensation circuit includes a first current mirror having a first branch coupled at the first node.