Abstract: A processor suitable for recursive computations is arranged to multiply successive input data words by a co-efficient word to produce results. It incorporates multiplier cells connected to form rows and columns. Each row is arranged to multiply a respective input data digit by the co-efficient. It begins with accumulator cells and continues with multiplier cells each arranged to multiply by an individual co-efficient digit and disposed in the row in descending order of digit significance. Columns other than the first column begin with a multiplier cell, and the higher significance columns terminate at respective accumulator cells. Any intervening multiplier cells are arranged in ascending order of multiplier digit significance. The processor employs radix 2 arithmetic. Each accumulator cell employs redundant radix 2 arithmetic, and each adds the highest significance transfer digit output of its row to at least three digits of equal and higher significance output from a preceding row.

Abstract: A digital processor for two's complement computations incorporates an array of multiplier cells each having the one-bit gated full adder logic function. The array has nearest-neighbour connections containing clock-activated latches for bit propagation. On each clock cycle, the cells receive input data, carry and cumulative sum bits. Each cell adds the carry and cumulative sum bits to the product of the data bit and a respective digit associated with the relevant cell. Data bits pass along array rows and sum bits accumulate in cascade down array columns. Carry bits are recirculated. Each coefficient digit is expressed as a sign bit and at least one magnitude bit consisting of or including a level bit. Each cell includes logic gates responsive to the sign and level bits, and carry a feedback latch and multiplier combination responsive to a least significant data bit flag to substitute the sign bit for a carry feedback bit.