Abstract: A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining a last accessor of the memory address, sending a cache probe to the last accessor, determining the last accessor no longer has a copy of the line; and sending a request for the previously accessed version of the line. The request may bypass the tag-directories and obtain the requested data from memory.

Abstract: A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received.

Abstract: In some implementations, a shared cache structure may be provided for sharing data among a plurality of processor cores. A data structure may be associated with the shared cache structure, and may include a plurality of entries, with each entry corresponding to one of the cache lines in the shared cache. Each entry in the data structure may further include a field to identify a processor core that most recently requested the data of the cache line corresponding to the entry. When a request for a particular cache line is received, a request for the data may be sent to a particular processor core identified in the data structure as the last accessor of the data.