Patents by Inventor Simon C. Steely

Simon C. Steely has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method to facilitate ordering point migration
    Patent number: 7818391
    Abstract: A system includes a first node that broadcasts a request for data. A second node having a first state associated with the data defines the second node as an ordering point for the data. The second node provides a response to the first node that transfers the ordering point to the first node in response to the request for the data.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: October 19, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stephen R. Van Doren, Gregory Edward Tierney, Simon C. Steely, Jr.
  • System and method to facilitate ordering point migration to memory
    Patent number: 7769959
    Abstract: A system may comprise a first node that includes an ordering point for data, the first node being operative to employ a write-back transaction associated with writing the data back to memory. The first node broadcasts a write-back message to at least one other node in the system in response to an acknowledgement provided by the memory indicating that the ordering point for the data has migrated from the first node to the memory.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: August 3, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stephen R. Van Doren, Gregory Edward Tierney, Simon C. Steely, Jr.
  • Dynamic quality of service (QoS) for a shared cache
    Patent number: 7725657
    Abstract: In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: William C. Hasenplaugh, Li Zhao, Ravishankar Iyer, Ramesh Illikkal, Srihari Makineni, Donald Newell, Aamer Jaleel, Simon C. Steely, Jr.
  • System and method for conflict responses in a cache coherency protocol
    Patent number: 7620696
    Abstract: A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response indicates that a second node has a pending broadcast read request for the data. A third node provides the requested data to the first node in response to the broadcast request from the first node. The first node fills the data provided by the third node in a cache associated with the first node.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: November 17, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stephen R. Van Doren, Gregory Edward Tierney, Simon C. Steely, Jr.
  • ADAPTIVE CONTROL OF MULTIPLE PREFETCHERS
    Publication number: 20080243268
    Abstract: According to one example embodiment of the inventive subject matter, there is provided a mechanism that controls which prefetchers are applied to execute an application in a computing system by turning them on and off. In one embodiment, this may be accomplished for example with a software control process that may run in the background. In another example embodiment, this may be accomplished using a hardware control machine, or a combination of hardware and software. The prefetchers are turned on and off in order to increase the performance of the computing system.
    Type: Application
    Filed: March 31, 2007
    Publication date: October 2, 2008
    Inventors: Meenakshi A. Kandaswamy, Simon C. Steely
  • Dynamic quality of service (QoS) for a shared cache
    Publication number: 20080235457
    Abstract: In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.
    Type: Application
    Filed: March 21, 2007
    Publication date: September 25, 2008
    Inventors: William C. Hasenplaugh, Li Zhao, Ravishankar Iyer, Ramesh Illikkal, Srihari Makineni, Donald Newell, Aamer Jaleel, Simon C. Steely
  • Systems and methods for employing speculative fills
    Patent number: 7409500
    Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative data fills that are provided in response to source requests. The multi-processor system may comprise a first cache that retains cache data associated with program instructions employing data from speculative data fills, and a second cache that retains cache data associated with data from speculative data fills that have been determined to be coherent.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: August 5, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney
  • Register file systems and methods for employing speculative fills
    Patent number: 7409503
    Abstract: Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a multi-processor system with a processor having a processor pipeline that executes program instructions with data from speculative fills that are provided in response to source requests. The multi-processor system may comprise a first register file that retains register values associated with program instruction employing data from speculative fills, and a second register file that retains register values associated with data from speculative fills that have been determined to be coherent.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: August 5, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney
  • Multi-processor systems and methods for backup for non-coherent speculative fills
    Patent number: 7406565
    Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request, and a backup system that retains information associated with a previous processor execution state corresponding to an instruction associated with the speculative fill. The backup system may initiate a backup of the processor pipeline to the previous processor execution state if the speculative fill is determined to be non-coherent, and the processor pipeline may continue execution of program instructions if the speculative fill is determined to be coherent.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: July 29, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney
  • System and method for conflict responses in a cache coherency protocol with ordering point migration
    Patent number: 7395374
    Abstract: Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: July 1, 2008
    Assignee: Hewlett-Packard Company, L.P.
    Inventors: Gregory Edward Tierney, Stephen R. Van Doren, Simon C. Steely, Jr.
  • Cache systems and methods for employing speculative fills
    Patent number: 7383409
    Abstract: One disclosed embodiment is a multi-processor system comprising a processor having a processor pipeline that executes program instructions with data from a speculative fill that is provided in response to a source request. The multi-processor system can further comprise a non-retired store cache that retains non-retired store data based on program instructions to store data into a data cache associated with the processor. The non-retired store data can be written to the data cache if data of a speculative fill associated with the non-retired store data is determined to be coherent. Other apparatus and methodologies are disclosed.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: June 3, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney
  • Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss
    Patent number: 7380107
    Abstract: Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor generates a speculative source request and a system source request in response to a cache miss. At least one processor provides a speculative data fill to a source processor in response to the speculative source request. The processor system provides a coherent data fill to the processor in response to the system source request.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: May 27, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney, Stephen R. Van Doren
  • Coherent signal in a multi-processor system
    Patent number: 7376794
    Abstract: Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source request by the source processor, and a coherent signal generated by the multi-processor system that provides an indication of which data fill of the at least one data fill is a coherent data fill.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: May 20, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney, Stephen R. Van Doren
  • Systems and methods for executing across at least one memory barrier employing speculative fills
    Patent number: 7360069
    Abstract: Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills that are provided in response to source requests, and a log that retains executed load instruction entries associated with executed program instruction. The executed load instruction entries may be retired if a cache line associated with data of the speculative data fill has not been invalidated in an epoch that is different from the epoch in which the executed load instruction is executed.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: April 15, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney
  • Source request arbitration
    Patent number: 7340565
    Abstract: Multiprocessor systems and methods are disclosed. One embodiment may comprise a plurality of processor cores. A given processor core may be operative to generate a request for desired data in response to a cache miss at a local cache. A shared cache structure may provide at least one speculative data fill and a coherent data fill of the desired data to at least one of the plurality of processor cores in response to a request from the at least one processor core. A processor scoreboard arbitrates the requests for the desired data. A speculative data fill of the desired data is provided to the at least one processor core. The coherent data fill of the desired data may be provided to the at least one processor core in a determined order.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: March 4, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Simon C. Steely, Jr., Gregory Edward Tierney
  • System and method for providing parallel data requests
    Patent number: 7240165
    Abstract: A multi-processor system includes a requesting node that provides a first request for data to a home node. The requesting node being operative to provide a second request for the data to at least one predicted node in parallel with first request. The requesting node receives at least one coherent copy of the data from at least one of the home node and the at least one predicted node.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: July 3, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregory Edward Tierney, Simon C. Steely, Jr.
  • Managing a multi-way associative cache
    Patent number: 7237067
    Abstract: Methods for storing replacement data in a multi-way associative cache are disclosed. One method comprises logically dividing the cache's cache sets into segments of at least one cache way; searching a cache set in accordance with a segment search sequence for a segment currently comprising a way which has not yet been accessed during a current cycle of the segment search sequence; searching the current segment in accordance with a way search sequence for a way which has not yet been accessed during a current way search cycle; and storing the replacement data in a first way which has not yet been accessed during a current cycle of the way search sequence. A cache controller that performs such methods is also disclosed.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: June 26, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Simon C. Steely, Jr.
  • System and method for responses between different cache coherency protocols
    Patent number: 7177987
    Abstract: Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a condition based on responses provided by the first node to requests provided according to a second cache coherency protocol, the second cache coherency protocol being different from the first cache coherency protocol. The first node provides a response to a given one of the requests to the first node that varies based on the condition detected by the detector.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: February 13, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stephen R. Van Doren, Gregory Edward Tierney, Simon C. Steely, Jr.
  • System and method for blocking data responses
    Patent number: 7149852
    Abstract: Systems and methods are disclosed for blocking data responses. One system includes a target node that, in response to a source broadcast request for requested data, provides a response that includes a copy of the requested data. The target node also provides a blocking message to a home node associated with the requested data. The blocking message being operative cause the home node to provide a non-data response to the source broadcast request if the blocking message is matched with the source broadcast request at the home node.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: December 12, 2006
    Assignee: Hewlett Packard Development Company, LP.
    Inventors: Stephen R. Van Doren, Gregory Edward Tierney, Simon C. Steely, Jr.
  • System and method for read migratory optimization in a cache coherency protocol
    Patent number: 7143245
    Abstract: A system comprises a first node including data having an associated D-state and a second node operative to provide a source broadcast requesting the data. The first node is operative in response to the source broadcast to provide the data to the second node and transition the state associated with the data at the first node from the D-state to an O-state without concurrently updating memory. An S-state is associated with the data at the second node.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: November 28, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregory Edward Tierney, Stephen R. Van Doren, Simon C. Steely, Jr.