Abstract: Data processing apparatus for executing successive data processing instructions comprises a processing core having a current operational state selected from a predetermined set of possible operational states, the current operational state being defined by a control state signal supplied to the core; a synchronous state machine circuit for generating an output state signal, indicating a provisionally valid next operational state of the core, in response to a predetermined phase of a current clock cycle of a clocking signal, the output state signal being dependent upon a current operational state of the core and control signals generated by the core before the predetermined phase of the current clock cycle indicative of a next data processing instruction to be executed by the core; and an asynchronous logic circuit for generating the control state signal in response to the output state signal and late control signals received after the predetermined phase of the current clock cycle.

Abstract: A CPU core 4 can operate at either an internal clock frequency fclk or an external clock frequency mclk. When operating at the internal clock frequency fclk, write request signals are buffered in a write buffer 10. When operating at the external clock frequency mclk, write request signals are unbuffered. In order to avoid write request signals reaching a signal bus 6 out of order, an interlock is provided between the two paths so that any pending write request signals in the write buffer 10 will serve to hold off any write request signals that may issue through the other path. When a write request signal generated at the external clock frequency is blocked, this serves to stall the CPU core 4 since the blocked external clock write request signal may give rise to an externally generated abort which would alter subsequent processing.