Abstract: A method for designing an optical system for providing reliable, robust and successful realization of a distortion variation function is presented. In a preferred embodiment, the proposed distortion variation optical system includes at least two non-symmetrical elements, which are moving in the transverse direction. The proposed freeform lens contains two transmissive refractive surfaces. The freeform elements designed with this method have preferably a flat surface and a non-symmetrical freeform surface. The two plano-surfaces are preferably made to face each other, so that a miniature camera can be offered. The value of the non-symmetrical freeform surface is used to produce variable optical power when the two freeform elements undergo a relative movement in the vertical direction. Using this method, an optical system with an active distortion, smaller form factor, and better imaging quality can be obtained.

Abstract: Heterocyclic entities that modulate PI3 kinase activity, pharmaceutical compositions containing the heterocyclic entities, and methods of using these chemical entities for treating diseases and conditions associated with PI3 kinase activity are described herein.

Abstract: A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.

Abstract: A method and system provide the ability to operate a three-dimensional (3D) computer animation and visual effects application (3D application). An interactive tutorial is initialized to perform an operation in the 3D application. The operation consists of a series of two or more steps and is a 3D animation, modeling, or visual effect operation. A text instruction for performing a first step of the two or more steps is displayed. User input is received, and a determination is made regarding whether the input successfully completes the first step. If not successfully completed, the tutorial waits for additional user input. If the user input results in a successful completion of the first step, the tutorial repeats until additional steps of the operation are also completed.

Abstract: An example device can include a computing device having a first portion of a pogo pin connector coupled thereto and a mount having a second portion of the pogo pin connector coupled thereto to receive the first portion of the pogo pin connector. The mount can be communicatively coupled to a hub for receiving signals sent from the computing device, and the signals can be communicated from the computing device to the hub via the pogo pin connector in response to engagement of the first portion with the second portion.

Abstract: Methods and apparatus for retargeting and prioritized interpolation of lens profiles. A lens profile file may include a set of lens sub-profiles. The camera body and/or settings described in the file may not exactly match that of camera body and/or settings used to capture a target image. A sub-profile processing module may perform a prioritized sub-profile sorting and interpolation method to generate an interpolated sub-profile that may be applied to the target image to correct aberrations including, but not limited to, geometric distortion, lateral chromatic aberration, and vignette. Thus, models generated for a reference camera at a variety of settings may be applied to a target image captured with the same type of lens but with a different camera and/or with different settings that are not exactly modeled in the lens profile file.

Abstract: A jewelry piece is disclosed which is constituted of an otherwise conventional jewelry item with a decorative body that defines the jewelry item, but which includes a trademark indicia appended to the decorative body and formed to appear as a part thereof. The trademark indicia includes a rearward located plate with a trademark, preferably registered, comprising one or more of a logo, a symbol, a word or words or a series of alphanumeric letters formed thereon and superimposed over the rearward plate an ornamental component that normally conceals the trademark indicia. The ornamental component of the trademark indicia is configured to be moveable relative to the rearward plate to expose the registered trademark.

Abstract: The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.

Abstract: A device may include a substrate, and an interlevel dielectric arranged over the substrate. The interlevel dielectric may include a first interlevel dielectric layer in an interconnect level i, the first interlevel dielectric layer having a first interconnect and a second interconnect therein. A nitride block insulator may be arranged over the first interlevel dielectric layer and over the first interconnect and the second interconnect. An opening may be arranged in the nitride block insulator, the opening extending through the nitride block insulator to expose a surface of the first interconnect in the first interlevel dielectric layer. A contact plug may be arranged in the opening of the nitride block insulator. The contact plug at least lines the opening and prevents out-diffusion of conductive material from the first interconnect. A thin film of a passive component may be arranged over the nitride block insulator and over the contact plug.

Abstract: Techniques and architectures for data modeling and management. Data modeling services are provided to agents within multiple different operating environments of a computing environment having at least one database stored on one or more physical memory devices communicatively coupled with one or more hardware processors the one or physical memory devices. Building and versioning of data modeling projects is coordinated and data utilized for the data modeling projects with the one or more hardware processors.

Abstract: Methods and compositions for generating haploid organisms are described.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing machine learning model training and deployment with a rollback mechanism within a computing environment.

Abstract: Techniques and architectures for data modeling and management. Data modeling services are provided to agents within multiple different operating environments of a computing environment having at least one database stored on one or more physical memory devices communicatively coupled with one or more hardware processors the one or physical memory devices. Building and versioning of data modeling projects is coordinated and data utilized for the data modeling projects with the one or more hardware processors.

Abstract: The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.

Abstract: Methods and compositions for generating haploid organisms are described.

Abstract: Techniques and architectures for data modeling and management. Data modeling services are provided to agents within multiple different operating environments of a computing environment having at least one database stored on one or more physical memory devices communicatively coupled with one or more hardware processors the one or physical memory devices. Building and versioning of data modeling projects is coordinated and data utilized for the data modeling projects with the one or more hardware processors.

Abstract: Methods and compositions for generating haploid organisms are described.

Abstract: Semiconductor memory devices and methods for writing data in memory cells are provided. An exemplary method for writing data in a memory cell includes providing the memory cell with a first pull-up transistor, a first power supply line coupled to the first pull-up transistor, a second pull-up transistor, and a second power supply line coupled to the second pull-up transistor. The method further includes applying a primary voltage from the first power supply line to the first pull-up transistor. The method also includes applying a secondary voltage from the second power supply line to the second pull-up transistor, wherein the secondary voltage is higher than the primary voltage. Further, the method includes performing a write operation to save a selected value in the memory cell.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing predictive engine evaluation and replay of engine performance.

Abstract: Semiconductor memory devices and methods for writing data in memory cells are provided. An exemplary method for writing data in a memory cell includes providing the memory cell with a first pull-up transistor, a first power supply line coupled to the first pull-up transistor, a second pull-up transistor, and a second power supply line coupled to the second pull-up transistor. The method further includes applying a primary voltage from the first power supply line to the first pull-up transistor. The method also includes applying a secondary voltage from the second power supply line to the second pull-up transistor, wherein the secondary voltage is higher than the primary voltage. Further, the method includes performing a write operation to save a selected value in the memory cell.