Abstract: A data processor which comprises a line of unit cells of alternating type, each capable of adopting two distinguishable states. The states of the cells of each respective type can be transformed (e.g. switched from one state to the other) by respective stimulae (which act on all cells of that type simultaneously) in dependence upon whether the cells two nearest neighbours in the line are both in mutually the same state or in mutually different states. Binary data bits are each represented by a pattern of states of four adjacent cells, and data is loaded onto the cells so that each bit is spaced by four cells from an adjacent bit. Logical operations can be performed on the data by loading a control unit (a particular pattern of states of six adjacent cells) and then applying the stimulae to transform the states of the cells. The processor can be implemented on a conventional computer by implementing the cells as Boolean variables in an array with the stimulae being update rules applied to the array.