Abstract: Within a data processing system having two alternative clock signals of different frequencies (fclk, mclk) it is necessary to provide a mechanism for switching between the clock signals. When switching from the fast clock (fclk) to the slow clock (mclk), the system adopts the slow clock from the first falling edge (ffe) after a processing delay (PD) associated with the decision as to whether or not to change clocks. This processing delay can be greater than one half of a cycle of the fast clock. In contrast, when switching from the slow clock to the fast clock, the system adopts the fast clock from the first rising edge (fre) following the processing delay. Thus, a system is provided in which differing strategies for synchronization are adopted depending upon the direction of change of the clock signal.