Abstract: A coprocessing core is provided with a unique architecture wherein the register block of the coprocessor is divided into a plurality of sub-blocks containing registers. In indirect addressing of the register block, the value loaded into a base pointer points to a particular one of the plurality of sub-blocks and activates the registers therein for read-write access. Changing of the base pointer value using only a single instruction brings another set of registers in a sub-block into activation. Unless relatively accessed, read only access is available to the registers in the register block. This architecture advantageously facilitates single instruction context switching, non-stacked machine operation and low latency interrupt handling. The architecture, as well as the programmability of the coprocessing core, further facilitates use of the device in a universal input/output controller application for connection between a host processor and plurality of different types and kinds of peripheral devices.

Abstract: The present invention discloses a method and system for providing a Finite State Machine (FSM) which is implemented within a telecommunications application program with the ability to transition from one state to another. The control of the transition being implemented by an Input/Output (I/O) Event Manager subsystem of a preemptive multi-tasking operating system.Additionally, the present invention discloses a method and system for providing a FSM which is implemented within a telecommunications application program with event driven control of physical devices having input and output capabilities. The event driven control being implemented by the I/O Event Manager subsystem.