Abstract: A method and apparatus are provided for conveying low level signals from a first circuit card to a second circuit card. The low level signals are encoded using a simple integer value N, and the low level signals are then communicated to the second circuit card as a sequence of N alternating values. A binary counter is used to generate the sequence of alternating values using the output of a single pin of the counter, although a second pin may be used to generate a clock signal. The invention allows all low level signals to be communicated in a robust yet simple way, minimizing the chance of spurious signals being generated upon hot insertion or extraction without complicated ad hoc solutions.

Abstract: A method and apparatus are provided for conveying low level signals from a first circuit card to a second circuit card. The low level signals are encoded using a simple integer value N, and the low level signals are then communicated to the second circuit card as a sequence of N alternating values. A binary counter is used to generate the sequence of alternating values using the output of a single pin of the counter, although a second pin may be used to generate a clock signal. The invention allows all low level signals to be communicated in a robust yet simple way, minimizing the chance of spurious signals being generated upon hot insertion or extraction without complicated ad hoc solutions.

Abstract: A circuit card connector arrangement is provided, wherein one of the connectors on the card is recessed relative to the other connectors. Using this arrangement, insertion and extraction detection of the card into another card is optimized without the need for a short pin on the other card. The recessed connector is the last connector on the card to make electrical contact with the other card upon insertion and the first connector to lose electrical contact with the other card upon extraction. Since the degree of recess and the choice of which connector is recessed is made by the designer of the inserted card rather than dependent on the design of the main card or board, such as a backplane, onto which the card is inserted, greater flexibility is possible in the design of the card and of the insertion/extraction circuitry on the card. In addition, insertion and extraction can be detected even if the main board does not have a short pin, such as occurs in some legacy system.

Abstract: One embodiment of the disclosures made herein is a method of detecting a transmission unit fault condition in a network system. In accordance with such a method, an operation is performed for designating transmission units received at a first counting location of a datapath, during a first duration consisting of a first specified counting interval and a first specified settling interval after the first specified counting interval elapses, as first designated transmission units. An operation is performed for determining a first datapath ingress transmission unit count for the first designated transmission units at a first counting location during the first duration. An operation is performed for determining a first datapath ingress transmission unit count, an operation is performed for determining a first datapath egress transmission unit count for the first designated transmission units at a second counting location of the datapath during the first duration.