Abstract: An arrangement for selecting the largest of a plurality of input currents (pma (k?1), pmb (k?1)) and adding a further current (Ibmk) to the selected current, the arrangement comprising: a plurality of inputs (901, 902) for receiving said input currents; a further input (905) for receiving said further current; an output (906, 907) for delivering an output current proportional to the sum of the largest of the input currents and the further current; means for feeding each of the received input currents to the main current conducting path of a respective transistor, (T900, T902) each of the transistors having its control electrode connected to a common point; a respective follower transistor (T901, T903) connected between the input and the common point; and a mirror transistor (T904) having its control electrode connected to the common point for producing a current whose value is related to that of the largest input current.

Abstract: An optical disk data decoder generates estimates of serial input signal values by slicing them into samples. The data sequences contained in each sample are detected. Successive samples are compared and used to increase or decrease the estimates. Such permits the center bit in a string of identical bits to be detected after subsequent bits have already been received and are being processed.

Abstract: An arrangement for generating an error signal representing the differences between an input signal voltage level (xpk, xnk) and an estimated value (rp, rn) for the input signal voltage level comprises first (T1, T2) and second (T5, T6) transconductors and a differencing circuit (T3, T4, T7, T8) which forms the modulus of the difference between the outputs of the transconductors. The error signal is converted into a probability signal by subtracting the error signal from a constant signal (408) to produce a signal at the output (407) which is a maximum when the input voltage level and estimated voltage level are equal.

Abstract: Apparatus for generating estimates of valid input signal values at sampling instants comprises a first data slicer (3) for slicing the input signal at a given level, data sequence detectors (205, 207) for detecting given data sequences in the input signal, second (301) and third (302) data slicers for slicing the input signal at signal values estimated for a given data bit of the given data sequences, memory elements (303, 304, 305; 306, 307, 308) for storing the outputs of the second (301) and third (302) data slicers when slicing the given data bit, and incrementing means (309, 311; 310, 312) for increasing or decreasing the estimated values depending on whether the stored outputs indicate the input signal value was above or below the estimated value when the given data bit was sliced by the second (301) or third (302) data slicer.

Abstract: An arrangement for generating an error signal representing the differences between an input signal voltage level (xpk, xnk) and an estimated value (rp, rn) for the input signal voltage level comprises first (T1, T2) and second (T5, T6) transconductors and a differencing circuit (T3, T4, T7, T8) which forms the modulus of the difference between the outputs of the transconductors. The error signal is converted into a probability signal by subtracting the error signal from a constant signal (408) to produce a signal at the output (407) which is a maximum when the input voltage level and estimated voltage level are equal.

Abstract: An arrangement for selecting the largest of a plurality of input currents (pma (k-1), pmb (k-1)) and adding a further current (Ibmk) to the selected current, the arrangement comprising: a plurality of inputs (901, 902) for receiving said input currents; a further input (905) for receiving said further current; an output (906, 907) for delivering an output current proportional to the sum of the largest of the input currents and the further current; means for feeding each of the received input currents to the main current conducting path of a respective transistor, (T900, T902) each of the transistors having its control electrode connected to a common point; a respective follower transistor (T901, T903) connected between the input and the common point; and a mirror transistor (T904) having its control electrode connected to the common point for producing a current whose value is related to that of the largest input current.

Abstract: A data slicer for data transmitted during given lines of a television signal comprises a subtractor to which the input data is applied at a first input and a slicing level is applied at a second input. The sliced data is fed to an offset generator which generates the slicing level. A transition detector controls a switch which causes the offset generator to generate either a fixed offset derived from a history of the received data amplitude or a zero offset. The arrangement is such that for teletext data a fixed offset is applied at the start of a line, zero offset is applied during the clock run in period, and a fixed offset is then used to slice the NRZ data. For biphase data such as VPS or PAL plus signalling data a zero offset is applied for the duration of the data packet.