Abstract: Integrated electronic device including: a semiconductor body of silicon delimited by a front surface and including at least a first semiconductive region of a first conductivity type, which extends into the semiconductor body starting from the front surface, and a second semiconductive region of a second conductivity type, which extends below the first semiconductive region; a dielectric capping region; a trench which extends through the dielectric capping region and through a front portion of the semiconductor body, in such a way that a part of the first semiconductive region laterally faces the trench, said trench partly extending inside the second semiconductive region; a conductive contact structure extending into the trench and including: a coating region of titanium silicide, which coats the bottom of the trench, in contact with the second semiconductive region, and also laterally coats the part of the first semiconductive region laterally facing the trench; and an inner conductive region.

Abstract: A laminated busbar for interconnecting electrical storage devices, comprising an insulating layer and at least one conductive band arranged on the insulating layer, the at least one conductive band comprising a succession of repeating conductor patterns, each conductor pattern defining a cluster having a first terminal and a second terminal for connection to an energy storage device. The laminated busbar also comprises a first terminator coupled to the first terminal and a second terminator coupled to the second terminal, the first and second terminators configured to connect to terminals of the energy storage device.

Abstract: In a module from an electrical battery, a laminated busbar interconnects prismatic electrical cells that are configured to be arranged in cell groups of the same number of cells. The busbar comprises: a first electrically conductive layer, with at least one electrically conducting element, each configured to connect electric poles of two adjacent cell groups, a first electrically insulating layer, laminated on the first conductive layer, a first electrical connector, configured to be connected to a first cell group, a second electrically conductive layer laminated onto the first insulating layer and comprising a second electrical connector to be connected to a last cell group, and a third electrical connector located closer to the first electrical connector than to the second electrical connector. The first insulating layer comprises a cut-out window, configured to allow electrical connection of the second electrical connector with the last cell group.

Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

Abstract: An assembly for a diaphragm pump includes: a body defining a plurality of diaphragm chambers spaced apart about a body axis, wherein each diaphragm chamber defines a membrane opening, an inlet chamber in fluid communication with each diaphragm chamber, and an outlet chamber in fluid communication with each diaphragm chamber; and a plurality of flexible membranes that each comprise an outer edge, wherein the body is configured to clamp the outer edge of each membrane along a corresponding membrane opening to seal a corresponding one of the diaphragm chambers; wherein the membranes are configured to deflect substantially in parallel to the body axis to suction fluid into each diaphragm chamber from the inlet chamber and discharge fluid from each diaphragm chamber into the outlet chamber; wherein each membrane comprises a coupling section configured to couple the membrane to a pump drive and arranged along a diaphragm axis that extends in parallel to the body axis, and a deflection section arranged radially outw

Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

Abstract: A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

Abstract: An integrated electronic circuit including: a dielectric body delimited by a front surface; A top conductive region of an integrated electronic circuit extend within a dielectric body having a front surface. A passivation structure including a bottom portion and a top portion laterally delimits an opening. The bottom portion extends on the front surface, and the top portion extends on the bottom portion. A field plate includes an internal portion and an external portion. The internal portion is located within the opening and extends on the top portion of the passivation structure. The external portion extends laterally with respect to the top portion of the passivation structure and contacts at a bottom one of: the dielectric body or the bottom portion of the passivation structure. The opening and the external portion are arranged on opposite sides of the top portion of the passivation structure.

Abstract: In a module from an electrical battery, a laminated busbar interconnects prismatic electrical cells that are configured to be arranged in cell groups of the same number of cells. The busbar comprises: a first electrically conductive layer, with at least one electrically conducting element, each configured to connect electric poles of two adjacent cell groups, a first electrically insulating layer, laminated on the first conductive layer, a first electrical connector, configured to be connected to a first cell group, a second electrically conductive layer laminated onto the first insulating layer and comprising a second electrical connector to be connected to a last cell group, and a third electrical connector located closer to the first electrical connector than to the second electrical connector. The first insulating layer comprises a cut-out window, configured to allow electrical connection of the second electrical connector with the last cell group.

Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

Abstract: A laminated busbar for interconnecting electrical storage devices, comprising an insulating layer and at least one conductive band arranged on the insulating layer, the at least one conductive band comprising a succession of repeating conductor patterns, each conductor pattern defining a cluster having a first terminal and a second terminal for connection to an energy storage device. The laminated busbar also comprises a first terminator coupled to the first terminal and a second terminator coupled to the second terminal, the first and second terminators configured to connect to terminals of the energy storage device.

Abstract: An integrated device includes a deep plug. The deep plug is formed by a deep trench extending in a semiconductor body from a shallow surface of a shallow trench isolation. A trench contact makes contact with a conductive filler of the deep trench through the shallow trench at its shallow surface. A system includes at least one integrated device with the deep plug. Moreover, a corresponding process for manufacturing this integrated device includes steps for forming and filling the deep trench before forming the shallow trench isolation and trench window through which the trench contact extends to make contact with the conductive filler. The semiconductor body has a thickness, and the deep trench extends into the semiconductor body less than the thickness.

Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

Abstract: A vertical-conduction semiconductor electronic device includes: a semiconductor body; a body region in the semiconductor body; a source terminal in the body region; a drain terminal spatially opposite to the source region; and a trench gate extending in depth in the semiconductor body through the body region and the source region. The trench gate includes a dielectric region of porous silicon oxide buried in the semiconductor body, and a gate conductive region extending between the dielectric region of porous silicon oxide and the first side.