Abstract: The semiconductor cooling arrangement comprises one or more semiconductor assemblies, a housing, and one or more baffles. Each semiconductor assembly comprises a heatsink, a semiconductor die, an encapsulant, and electrical connections. The semiconductor die is bonded to the heatsink and contains a semiconductor power device. The encapsulant covers the semiconductor die. The side of the heatsink to which the semiconductor die is bonded extends beyond the encapsulant. The electrical connections pass through the encapsulant and to the semiconductor die. The housing has a chamber for housing the one or more assemblies. Each baffle comprises through-holes arranged such that fluid flows through the through-holes to a region of a respective semiconductor assembly to which the semiconductor power device is mounted, or to a region of the heatsink of the semiconductor assembly opposite a location to which the semiconductor power device is mounted.

Abstract: Described herein is a method of cooling a plurality of power devices, where the power devices are arranged as a plurality of switches used to generate a three-phase output AC voltage. Based on power device stress data, one or more switches (associated with one or more phase output AC voltages) may be identified as requiring more cooling than other of the switches. The switches are controlled to apply a common mode component voltage to each of the three phases for at least a portion of one or more output AC voltage segments. The common mode component voltage has a maximum amplitude that is sufficient to clamp the phase AC output voltage of the identified phase(s) to the positive supply rail voltage and/or negative rail supply voltage when the respective phase AC voltage is approaching respectively the positive supply rail voltage or negative supply rail voltage to cool the identified switch(es).

Abstract: We describe techniques to reduce DC ripple voltage in an inverter by determining a plurality of switching events for each of the three phases in each Pulse Width Modulation (PWM) period. The switching events provide a desired target output voltage for the respective PWM period. From this determination of the switching events, a comparison can be made to determine a first time period between a first and second switching event across all of the phases, and a second time period between the second and a third switching event across all of the phases. The timing of one or more switching events in only one of the phases in the respective PWM period is adjusted in response to the determined time period being greater than a threshold in order to reduce the determined first or second time period.

Abstract: A modulation technique is described in which a controller modulates the output AC voltages to introduce an offset to the phase that is most positive or most negative such that the phase is clamped to the +dc supply when the respective phase is most positive and to the ?dc supply rail when most negative. The offset is provided by introducing a common mode component voltage to all of the phases over a plurality of output angle segments. In order to reduce the Noise Vibration and Harshness (NVH) and EMI, the common mode component voltage amplitude is varied over the output angles within the respective segment between a minimum and a maximum in order to control a slew rate of the rising or falling edges of the three phase AC output voltages.

Abstract: Described herein is a method of cooling a plurality of power devices, where the power devices are arranged as a plurality of switches used to generate a three-phase output AC voltage. Based on power device stress data, one or more switches (associated with one or more phase output AC voltages) may be identified as requiring more cooling than other of the switches. The switches are controlled to apply a common mode component voltage to each of the three phases for at least a portion of one or more output AC voltage segments. The common mode component voltage has a maximum amplitude that is sufficient to clamp the phase AC output voltage of the identified phase(s) to the positive supply rail voltage and/or negative rail supply voltage when the respective phase AC voltage is approaching respectively the positive supply rail voltage or negative supply rail voltage to cool the identified switch(es).

Abstract: A semiconductor cooling arrangement. The semiconductor cooling arrangement comprises one or more semiconductor assemblies, a housing, and one or more baffles. Each assembly comprises a heatsink and one or more semiconductor power devices mounted on and thermally coupled to the heatsink. The housing is for housing the one or more assemblies in a chamber within the housing, and comprises inlet and outlet ports in fluid communication with the chamber. The baffles are arranged such that fluid flows through each baffle to a respective heatsink. Each baffle comprises through-holes arranged such that fluid flows through the through holes to a region of the semiconductor assembly to which a semiconductor power device is mounted, or to a region of the heatsink opposite a location to which a semiconductor power device is mounted.

Abstract: A modulation technique is described in which a controller modulates the output AC voltages to introduce an offset to the phase that is most positive or most negative such that the phase is clamped to the +dc supply when the respective phase is most positive and to the ?dc supply rail when most negative. The offset is provided by introducing a common mode component voltage to all of the phases over a plurality of output angle segments. In order to reduce the Noise Vibration and Harshness (NVH) and EMI, the common mode component voltage amplitude is varied over the output angles within the respective segment between a minimum and a maximum in order to control a slew rate of the rising or falling edges of the three phase AC output voltages.

Abstract: A cooling arrangement, for cooling power devices such as semiconductor power devices, comprises a housing having sidewalls around the periphery of a baseplate, and a capping plate opposing the baseplate. The housing forms a cavity through which cooling fluid may flow between an inlet and an outlet disposed in the housing. Within the cavity is provided one or more baffles that are arranged to force the cooling fluid flowing between the inlet and outlet along a labyrinthine path through the cavity. At least one of the baffles comprises at least one through-hole, which permit cooling fluid to pass there through from one side of the baffle to the other.

Abstract: We describe techniques to reduce DC ripple voltage in an inverter by determining a plurality of switching events for each of the three phases in each Pulse Width Modulation (PWM) period. The switching events provide a desired target output voltage for the respective PWM period. From this determination of the switching events, a comparison can be made to determine a first time period between a first and second switching event across all of the phases, and a second time period between the second and a third switching event across all of the phases. The timing of one or more switching events in only one of the phases in the respective PWM period is adjusted in response to the determined time period being greater than a threshold in order to reduce the determined first or second time period.

Abstract: A semiconductor arrangement and an inverter incorporating the semiconductor arrangement, in particular to an inverter for use with traction power units e.g. for on and off road vehicles and stationary power inversion, are described. In the arrangement, semiconductor devices are thermally and electrically coupled to a heatsink as a module. The heatsink is configured as a bus bar to electrically connect the one or more semiconductor devices together to transmit power between the one or more semiconductor devices. The semiconductor devices may be cooled using the structure to which they are attached, and also immersed in a cooling medium to further increase the cooling of the device.

Abstract: A gate driver for a semiconductor power device and a method of driving the gate of a semiconductor power device. The current flowing through the semiconductor power device, caused by a first gate drive voltage during the present switching cycle, is sensed. Based on a second drive signal to be used in the next switching cycle, a second current is determined for that second drive signal, which are then compared to an EMC model. The EMC model defines a plurality of EMC values for respective gate drive voltages and currents conducted through the semiconductor power device. A gate drive voltage adjustment value is selected from a plurality of gate drive voltage adjustment values in the EMC model based on the predicted EMC value generated by the semiconductor power device when being driven using the second drive voltage and conducting the second current. The second gate drive voltage is adjusted using the selected gate drive voltage adjustment value for the next switching cycle.

Abstract: The present invention relates to a semiconductor cooling arrangement for cooling semiconductor devices, such as power semiconductors. The semiconductor cooling arrangement comprises one or more semiconductor assemblies located in a chamber within a housing. The housing comprises inlet and outlet ports for receiving and outputting a cooling medium. The chamber is flooded with a cooling medium to cool the assemblies. The assemblies themselves each comprise a heatsink and one or more semiconductor power devices thermally coupled to the heatsink. The heatsink comprises heat exchanging elements in the form of a plurality of holes in the heatsink extending through the heatsink from one surface to another surface such that the cooling medium flows through the holes to extract heat from the heatsink.

Abstract: A semiconductor arrangement and an inverter incorporating the semiconductor arrangement, in particular to an inverter for use with traction power units e.g. for on and off road vehicles and stationary power inversion, are described. In the arrangement, semiconductor devices are thermally and electrically coupled to a heatsink as a module. The heatsink is configured as a bus bar to electrically connect the one or more semiconductor devices together to transmit power between the one or more semiconductor devices. The semiconductor devices may be cooled using the structure to which they are attached, and also immersed in a cooling medium to further increase the cooling of the device.

Abstract: The present invention relates to a semiconductor cooling arrangement for cooling semiconductor devices, such as power semiconductors. The semiconductor cooling arrangement comprises one or more semiconductor assemblies located in a chamber within a housing. The housing comprises inlet and outlet ports for receiving and outputting a cooling medium. The chamber is flooded with a cooling medium to cool the assemblies. The assemblies themselves each comprise a heatsink and one or more semiconductor power devices thermally coupled to the heatsink. The heatsink comprises heat exchanging elements in the form of a plurality of holes in the heatsink extending through the heatsink from one surface to another surface such that the cooling medium flows through the holes to extract heat from the heatsink.

Abstract: A drive controller for a motor of a compressor includes a drive circuit that applies voltages to windings of the motor. The drive controller includes a speed control module that controls the drive circuit to rotate the motor at a requested speed. The drive controller includes a speed determination module that generates the requested speed. The drive controller includes a defrost module that enables a defrost mode in response to a defrost command. While the defrost mode is enabled, the defrost module causes the speed determination module to (i) ramp the requested speed down from a speed demand to a defrost speed and (ii) maintain the requested speed at the defrost speed for a predetermined period of time.

Abstract: Embodiments of the present invention relate to an a method, apparatus and computer program product for controlling the operation of a drive unit comprising a plurality of switching modules arranged to receive a DC electricity supply and generate an AC electricity supply for driving a load from the received DC electricity supply, the AC electricity supply being generated by the switching of the plurality of switching modules between a conducting state and a non-conducting state. The method comprises receiving one or more characteristics associated with each of the switching modules, comparing, for each switching module of the plurality of switching modules, a characteristic of the switching module with an equivalent characteristic associated with one or more other switching modules of the plurality of switching modules, and controlling a time period during which one or more of the plurality of switching modules are in the conducting state in accordance with a result of the comparison.

Abstract: A method and a control system for a multiphase-phase inverter system, the control system comprising an electric current detection circuit and a processor, wherein each phase of an electrical cycle is separated into a plurality of sections, inputs from the electric current detection circuit are received, each input indicating a measured phase current, and a phase current is calculated in each section, wherein the phase current calculation in at least one of the sections is determined from a changing ratio of the value of the phase current calculated from the measured values of the other phase currents in the multiphase system and the measured value of the phase.

Abstract: There is provided a method and control system for controlling a switching device in a power converter according to a modulation scheme. The switching device couples a direct current (DC) source to provide an alternating current (AC) output at a particular switching frequency. The method comprises the step of, in each switching period, switching the switching device between active configurations providing a finite voltage at the output and inactive configurations providing a zero voltage at the output. The ratio between the total period of time in which the switching device is in an active configuration and the total period of time in which the switching device is in an inactive configuration is the same for each switching period and is determined according to the desired voltage at the AC output.

Abstract: The present disclosure relates to a power conversion system comprising a transformer comprising first, second, and third inductive coupling elements, a first power supply arranged to provide a voltage across the first coupling element, a second power supply arranged to provide a voltage across the second coupling element, an output arranged to receive a voltage from the third coupling element. In use, the voltage across the first coupling element and the voltage across the second coupling element are arranged to induce a voltage in the third coupling element. The system also comprises a control arrangement arranged to independently control the operation of the first and second power supplies.

Abstract: A supply voltage compensation circuit comprising a processor arranged to sense a signal indicative of a supply voltage on an input wherein if the signal indicates that the supply voltage is under a predetermined threshold, the processor is arranged to provide an output signal arranged to couple an auxiliary energy source to provide voltage compensation for supply under voltage.