Patents by Inventor Simon Deeley

Simon Deeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190310710
    Abstract: A system and method for the development, encapsulation, distribution and deployment of low-latency input-output processing algorithms to mediate human-computer interaction by generating haptic feedback influenced in real time by external stimuli. The invention provides the ability to design algorithms that scale or are otherwise automatically adjusted when deployed to computing environments with different capabilities. The invention also provides features to facilitate the design, sharing and modification of the algorithms, thereby reducing development time/cost.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 10, 2019
    Inventors: Simon Deeley, Hamish Milne, Brygida Dzidek
  • Publication number: 20190196591
    Abstract: Strategies for managing an “always on” solution for volumes with enhanced interactive haptic feedback and its implications are addressed. Ultrasound transducer arrays may be mounted on a person (such as on a head mounted display or other wearable accessory). This array may utilize some form of 6 degree-of-freedom tracking for both the body and hands of the user. The arrays coordinate to project focused acoustic pressure at specific locations on moving hands such that a touch sensation is simulated. Using wearable microphones, the ultrasonic signal reflected and transmitted into the body can be used for hand and gesture tracking.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Inventors: Benjamin John Oliver Long, Simon Deeley, William Wren, Brian Kappus
  • Patent number: 8058896
    Abstract: A programming interface device for a programmable logic circuit comprises a series of parallel logic block chains each having first and second connection means, the first and second connection means being disposed at opposite ends of each chain. The programming interface device comprises first and second interfacing means for interfacing with the first and second connection means of each logic block chain, respectively and at least one programming circuit, each programming circuit arranged to configure a plurality of serially connected logic blocks. Finally, the programming interface comprises programmable connection means for connecting the connection means of each logic block chain to either the connection means of another logic block chain or directly to one of the at least one programming circuits, such that the parallel logic block chains can be configured in parallel, series or in any combination thereof.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: November 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Simon Deeley, Anthony Stansfield
  • Publication number: 20100090720
    Abstract: A programming interface device for a programmable logic circuit, the programmable logic circuit comprising a series of parallel logic block chains each having first and second connection means, the first and second connection means being disposed at opposite ends of each chain. The programming interface device comprising first and second interfacing means for interfacing with the first and second connection means of each logic block chain, respectively and at least one programming circuit, each programming circuit arranged to configure a plurality of serially connected logic blocks. Finally, the programming interface comprises programmable connection means for connecting the connection means of each logic block chain to either the connection means of another logic block chain or directly to one of the at least one programming circuits, such that the parallel logic block chains can be configured in parallel, series or in any combination thereof.
    Type: Application
    Filed: October 8, 2009
    Publication date: April 15, 2010
    Inventors: Simon Deeley, Anthony Stansfield
  • Patent number: 7679400
    Abstract: An apparatus for and method of programming a programmable logic device, the programmable logic device comprising a plurality of serially connected programmable logic regions. The method comprises the steps of receiving initial programming data for programming the plurality of serially connected programmable logic regions and receiving transformation data related to the presence and location of at least one faulty serially connected programmable logic region. The method also comprises the steps of generating bypass programming data which, in use, renders a serially connected programmable logic region logically invisible and generating effective programming data by incorporating, using information found in the transformation data, the bypass programming data into the initial programming data.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: March 16, 2010
    Assignee: Panasonic Corporation
    Inventor: Simon Deeley