Abstract: Methods of verifying a property of a hardware design for an integrated circuit to implement a product of power functions of the form x0t0× . . . ×xntn, wherein t0 . . . tn are fixed, rational numbers, x0 . . . xn are floating point inputs, and n is an integer greater than or equal to one. A first verification phase comprises formally verifying that, for any first non-exception input set X=X0, . . . , Xn and any second non-exception input set Y=Y0, . . . , Yn in an input space wherein corresponding inputs have a same mantissa and (t0X0.exp+ . . . +tnXn.exp)?(t0Y0.exp+ . . . +tnYn.exp) is an integer, an instantiation of the hardware design generates outputs X? and Y? with a same mantissa and X?exp?(t0X0.exp+ . . . +tnXn.exp)=Y?exp?(t0Y0.exp+ . . . +tnYn.exp); and second verification phase comprises verifying the property for the hardware design for a subset of input sets in the input space, the subset of input sets selected based on exponents sets wherein (t0X0.exp+ . . . +tnXn.exp)?(t0Y0.exp+ . . . +tnYn.

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.