Patents by Inventor Simon H. Friedmann
Simon H. Friedmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11182293Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.Type: GrantFiled: December 5, 2019Date of Patent: November 23, 2021Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
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Publication number: 20200110702Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
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Patent number: 10592414Abstract: Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from the cache is retrieved. A determination is made whether the current request is seeking the same data from the cache as at least one of the one or more previous requests. A further determination is made whether the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to a processing unit when seeking access. A next cache write access is suppressed if the at least one of previous requests seeking the same data was successful in arbitrating access to the processing unit.Type: GrantFiled: July 14, 2017Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Girish G. Kurup, Markus Kaltenbach, Ulrich Mayer, Martin Recktenwald
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Patent number: 10585797Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.Type: GrantFiled: July 14, 2017Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
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Patent number: 10572384Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.Type: GrantFiled: December 28, 2017Date of Patent: February 25, 2020Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
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Patent number: 10268582Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.Type: GrantFiled: February 14, 2018Date of Patent: April 23, 2019Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
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Publication number: 20190018771Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.Type: ApplicationFiled: February 14, 2018Publication date: January 17, 2019Inventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
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Publication number: 20190018769Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.Type: ApplicationFiled: July 14, 2017Publication date: January 17, 2019Inventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
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Publication number: 20190018779Abstract: Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from the cache is retrieved. A determination is made whether the current request is seeking the same data from the cache as at least one of the one or more previous requests. A further determination is made whether the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to a processing unit when seeking access. A next cache write access is suppressed if the at least one of previous requests seeking the same data was successful in arbitrating access to the processing unit.Type: ApplicationFiled: July 14, 2017Publication date: January 17, 2019Inventors: Simon H. Friedmann, Girish G. Kurup, Markus Kaltenbach, Ulrich Mayer, Martin Recktenwald
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Publication number: 20190018770Abstract: A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.Type: ApplicationFiled: December 28, 2017Publication date: January 17, 2019Inventors: Simon H. Friedmann, Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Anthony Saporito
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Patent number: 10169233Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.Type: GrantFiled: June 5, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
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Patent number: 10169234Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.Type: GrantFiled: October 23, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
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Publication number: 20180349277Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.Type: ApplicationFiled: June 5, 2017Publication date: December 6, 2018Inventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
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Publication number: 20180349278Abstract: A method and computer processor performs a translation lookaside buffer (TLB) purge with concurrent cache updates. Each cache line contains a virtual address field and a data field. A TLB purge process performs operations for invalidating data in the primary cache memory which do not conform to the current state of the translation lookaside buffer. Whenever the TLB purge process and a cache update process perform a write operation to the primary cache memory concurrently, the write operation by the TLB purge process has no effect on the content of the primary cache memory and the cache update process overwrites a data field in a cache line of the primary cache memory but does not overwrite a virtual address field of said cache line. The translation lookaside buffer purge process is subsequently restored to an earlier state and restarted from the earlier state.Type: ApplicationFiled: October 23, 2017Publication date: December 6, 2018Inventors: Simon H. Friedmann, Markus Kaltenbach, Dietmar Schmunkamp, Johannes C. Reichart
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Patent number: 10089231Abstract: Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from the cache is retrieved. A determination is made whether the current request is seeking the same data from the cache as at least one of the one or more previous requests. A further determination is made whether the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to a processing unit when seeking access. A next cache write access is suppressed if the at least one of previous requests seeking the same data was successful in arbitrating access to the processing unit.Type: GrantFiled: November 7, 2017Date of Patent: October 2, 2018Assignee: International Business Machines CorporationInventors: Simon H. Friedmann, Girish G. Kurup, Markus Kaltenbach, Ulrich Mayer, Martin Recktenwald