Abstract: A phase-locked loop (PLL) 1 is provided with means for changing the frequency of the output signal to a desired frequency. The PLL 1 is operated during a first period with a feedback frequency division ratio set to an initial value N′ which controls the conduction time of the charge pumps during a first period having a predetermined length to place an amount of charge on the loop filter 6 during the first period sufficient to produce a control voltage for controlling the voltage-controlled oscillator 10 to output an output signal substantially at the desired output frequency. At the end of the first period, the feedback loop 11 is opened by disabling the charge pump 5 for a second period to allow the control voltage output from the loop filter 6 to settle. Subsequently the feedback loop 6 is closed and the feedback frequency division ratio is set to a proper value N2 such that operation of the PLL 1 subsequent to the second period locks the output frequency to the desired frequency.

Abstract: A charge pump pair implemented by CMOS transistors comprises two charge pumps switchable to output a current of positive and negative polarity, respectively. Each charge pump comprises a current mirror including a reference current source, a logging transistor supplied with a reference current from the reference current source and a mirror transistor, the gate of the mirror transistor being connected to the gate of the logging transistor circuit to mirror an image of the reference current as the output of the charge pump. Each charge pump further include a clamp transistor switchable to selectively clamp the control input of the mirror transistor to switch the output of the mirror transistor on and off. The charge pumps are relatively scaled to equalize the rise time constants of the transient outputs of the charge pumps when switched on and the fall time constants of the transient outputs of the charge pumps when switched off.

Abstract: A phase-locked loop (PLL) 1 is provided with means for changing the frequency of the output signal to a desired frequency. The PLL 1 is operated during a first period with a feedback frequency division ratio set to an initial value N′ which controls the conduction time of the charge pumps during a first period having a predetermined length to place an amount of charge on the loop filter 6 during the first period sufficient to produce a control voltage for controlling the voltage-controlled oscillator 10 to output an output signal substantially at the desired output frequency. At the end of the first period, the feedback loop 11 is opened by disabling the charge pump 5 for a second period to allow the control voltage output from the loop filter 6 to settle. Subsequently the feedback loop 6 is closed and the feedback frequency division ratio is set to a proper value N2 such that operation of the PLL 1 subsequent to the second period locks the output frequency to the desired frequency.