Patents by Inventor Simon Hermann Friedmann

Simon Hermann Friedmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135083
    Abstract: Disclosed herein is a computer implemented method of correcting a timing failure of a network of conductors and repowering structures in an integrated circuit design using a reinforcement learning agent. The reinforcement learning agent comprises a neural network. The method comprises: receiving a graph comprising nodes and edges that encodes said network of conductors and repowering structures; and receiving a modification recommendation from said reinforcement learning agent in response to inputting said graph into said reinforcement learning agent.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 25, 2024
    Inventors: Gregor Boronowsky, Marvin von der Ehe, Manuel Beck, Jan Niklas Stegmaier, Simon Hermann Friedmann
  • Patent number: 11775444
    Abstract: Driving address translations in a microprocessor system by sending a rejected Lx+1 cache request from a first set of caches of a first level Lx to a central request unit, transferring an Lx+1 cache request having a translation of a virtual address into a physical address stored in a first buffer, from the central request unit to the at least one Lx+1 cache, and keeping an Lx+1 cache request lacking a translation of a virtual address into a physical address stored in the first buffer, pending in the central request unit.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: October 3, 2023
    Assignee: International Business Machines Corporation
    Inventors: Willm Hinrichs, Markus Kaltenbach, Simon Hermann Friedmann, Joerg Deutschle, Thomas G. Koehler
  • Publication number: 20230297515
    Abstract: Driving address translations in a microprocessor system by sending a rejected Lx+1 cache request from a first set of caches of a first level Lx to a central request unit, transferring an Lx+1 cache request having a translation of a virtual address into a physical address stored in a first buffer, from the central request unit to the at least one Lx+1 cache, and keeping an Lx+1 cache request lacking a translation of a virtual address into a physical address stored in the first buffer, pending in the central request unit.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 21, 2023
    Inventors: Willm Hinrichs, Markus Kaltenbach, Simon Hermann Friedmann, Joerg Deutschle, Thomas G. Koehler