Abstract: A call path identifier is maintained which is permuted in response to a calling instruction for calling a target function, based on a function return address. The call path identifier is used as a modifier value for authentication code generating and checking instructions for generating and checking authentication codes associated with source values. In response to the authentication code checking instruction, if an expected authentication code mismatches a previously generated authentication code for a source value then an error handling response is triggered. This is useful for preventing attacks where address pointers which are valid in one part of the code are attempted to be reused in other parts of code.

Abstract: Various encoding schemes are discussed for more efficiently encoding instructions which identify first and second architectural register numbers. In the first example, by constraining the first architectural register number to be greater than the second architectural register number, this frees up encodings for use in encoding other operations. In a second example, the first and second architectural register numbers may take any value but one of a first type of processing operation and a second type of processing operation is selected depending on a comparison of the first and second architectural register numbers.

Abstract: A call path identifier is maintained which is permuted in response to a calling instruction for calling a target function, based on a function return address. The call path identifier is used as a modifier value for authentication code generating and checking instructions for generating and checking authentication codes associated with source values. In response to the authentication code checking instruction, if an expected authentication code mismatches a previously generated authentication code for a source value then an error handling response is triggered. This is useful for preventing attacks where address pointers which are valid in one part of the code are attempted to be reused in other parts of code.

Abstract: A data processing apparatus is provided. Call path storage circuitry stores an identifier of a call path and processing circuitry executes a current group of instructions from a plurality of groups of instructions. The processing circuitry is responsive to a calling instruction to firstly cause the processing circuitry to start executing, in dependence on the calling instruction, a next group of instructions from the plurality of groups of instructions such that the current group of instructions is added to the call path, and to secondly cause the call path storage circuitry to update the identifier of the call path, on the basis of the call path, using a compression algorithm.

Abstract: An apparatus comprises processing circuitry to generate a result vector including at least one N-bit data element in response to an element size increasing instruction identifying at least a first input vector including M-bit data elements, where N>M. First and second forms of the element size increasing instruction are provided for generating the result vector using first and second subsets of data elements of the first input vector respectively. Positions of the first and second subsets of data elements in the first input vector are interleaved.

Abstract: A data processing apparatus is provided. Call path storage circuitry stores an identifier of a call path and processing circuitry executes a current group of instructions from a plurality of groups of instructions. The processing circuitry is responsive to a calling instruction to firstly cause the processing circuitry to start executing, in dependence on the calling instruction, a next group of instructions from the plurality of groups of instructions such that the current group of instructions is added to the call path, and to secondly cause the call path storage circuitry to update the identifier of the call path, on the basis of the call path, using a compression algorithm.

Abstract: Various encoding schemes are discussed for more efficiently encoding instructions which identify first and second architectural register numbers. In the first example, by constraining the first architectural register number to be greater than the second architectural register number, this frees up encodings for use in encoding other operations. In a second example, the first and second architectural register numbers may take any value but one of a first type of processing operation and a second type of processing operation is selected depending on a comparison of the first and second architectural register numbers.

Abstract: An apparatus comprises processing circuitry to generate a result vector including at least one N-bit data element in response to an element size increasing instruction identifying at least a first input vector including M-bit data elements, where N>M. First and second forms of the element size increasing instruction are provided for generating the result vector using first and second subsets of data elements of the first input vector respectively. Positions of the first and second subsets of data elements in the first input vector are interleaved.