Patents by Inventor Simon J. Craske

Simon J. Craske has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data processing apparatus and method for providing target address information for branch instructions
    Patent number: 8635406
    Abstract: A data processing apparatus and method have a processor for executing instructions, and a prefetch unit for prefetching instructions from memory prior to sending those instructions to the processor for execution. A branch target cache structure has a plurality of entries, where the cache structure comprises an initial branch target cache having a first number of entries and a promoted entry branch target cache having a second number of entries. During lookup operation, both the initial entry branch target cache and the promoted entry branch target cache are accessed in parallel. For a branch instruction executed by the processor that does not currently have a corresponding entry in the branch target cache structure, allocation circuitry performs an initial allocation operation to allocate one of the entries in the initial entry branch target cache for storing the branch instruction information for that branch instruction.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: January 21, 2014
    Assignee: ARM Limited
    Inventors: Peter R Greenhalgh, Simon J Craske
  • DATA PROCESSING APPARATUS AND METHOD FOR PROVIDING TARGET ADDRESS INFORMATION FOR BRANCH INSTRUCTIONS
    Publication number: 20130238858
    Abstract: A data processing apparatus and method have a processor for executing instructions, and a prefetch unit for prefetching instructions from memory prior to sending those instructions to the processor for execution. A branch target cache structure has a plurality of entries, where the cache structure comprises an initial branch target cache having a first number of entries and a promoted entry branch target cache having a second number of entries. During lookup operation, both the initial entry branch target cache and the promoted entry branch target cache are accessed in parallel. For a branch instruction executed by the processor that does not currently have a corresponding entry in the branch target cache structure, allocation circuitry performs an initial allocation operation to allocate one of the entries in the initial entry branch target cache for storing the branch instruction information for that branch instruction.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Inventors: Peter R. GREENHALGH, Simon J. Craske