Abstract: A digital frequency up conversion arrangement comprising a source of fixed high speed clock pulses the frequency of which is near to the desired output frequency of the converter arrangement, a high frequency counter to which the clock pulses are applied to produce a repetitive fixed m-bit digital word in parallel output form, the sample rate of the m-bit word being equal to the high speed clock frequency, divider to which the high speed clock pulses are applied to form a slow clock pulse train, a slow frequency NCO to which the slow clock train is applied together with frequency control signals to produce m-bit words the sample rate of which is equal to the slow clock frequency, summing means to which the high sample rate and slow sample rate m-bit words are applied to produce resultant m-bit words which form a digital representation of a sine wave at the required output frequency, and digital-to-analog conversion means to which the resultant m-bit words are applied to produce an analog sine wave at the requ

Abstract: A code correlation arrangement comprising clock means for sampling (11) an analogue input signal, means for generating a digital code sequence (14), means for clocking (15) the code generating means synchronously with the sampling of the analogue input signal, means for digitally multiplying (12) the code sequence with the sampled analogue signal, means for digitally filtering (13) the output of the multiplying means, and means for controlling the clock phase of the code generating means to maintain phase tracking of an incoming code phase in the analogue signal by the code generating means.

Abstract: A method and apparatus for effecting phase rotation of a digital signal by applying said digital signal as partial address signals for a look-up table in a memory together with rotation control signals forming additional address signals whereby the memory output represents the phase rotated signal, characterized in that each input vector is modified so that points representing digitized input vector values plotted on a rectangular coordinate grid are transformed to lie on an alternative coordinate system and the rotated vectors are retransformed and requantized to a digital output.

Abstract: Phase rotation of an input digital signal is effected by applying the input signal to a look-up table in a memory together with a rotation control signal. The output of the memory is the phase rotated signal. To reduce the size of the PROM required for the look-up table advantage is taken of the symmetry of the quadrants through which the signal may be rotated. With a maximum 0.degree. to 360.degree. phase rotation range divided into four 90.degree. quadrants a look-up table is only required for one quadrant. Thus the quadrant which the input signal is in is determined and the input signal transformed to correspond to the one quadrant by simple logic external to the PROM.

Abstract: A NAVSTAR receiver in which the received signals are processed to produce digitized quadrature signals at zero i.f. Baseband phasor rotation to effect Doppler tracking in the receiver loop is accomplished by deriving digital signals representing sin .omega.T and cos .omega.T for the required rotation angle .omega.T, multiplying the quadrature signals separately and summing the outputs according to the algorithm I.sup.1 =I cos .omega.T+Q sin .omega.T and Q.sup.1 =Q cos .omega.T-I sin .omega.T, where I & Q are the digitized quadrature signals.

Abstract: A receiver for a Navstar satellite navigation system wherein the satellite signals are down converted into zero i.f. quadrature signals (70a, 70b) and digitized (71a, 71b). The digitized signals address a PROM (72) together with additional bits representing phase rotation information (74) and locally generated code signals (e,l,p). The PROM is loaded with data in the form of "look-up" tables incorporating combinations of all input signal conditions whereby the combined address signals effect correlation and phase rotation simultaneously of the received signals.