Abstract: A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.

Abstract: A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.

Abstract: A digital phase locked loop (PLL) for recovering a stable clock signal from at least one input signal subject to jitter. The PLL has a digital controlled oscillator for generating a desired output and a stable local oscillator or providing clock signals. A plurality of hierarchical, multi-stage delay lines are provided to generate the required output frequencies for stable T1, E1 and ST3/OC3 timing references.

Abstract: A digital phase locked loop (PLL) for recovering a stable clock signal from at least one input signal subject to jitter. The PLL has a digital controlled oscillator for generating a desired output and a stable local oscillator or providing clock signals. A plurality of hierarchical, multi-stage delay lines are provided to generate the required output frequencies for stable T1, E1 and ST3/OC3 timing references.

Abstract: A frequency doubler for receiving an input clock signal and generating an output signal at twice the input signal frequency and having fifty percent duty cycle. The input signal is received by a tapped delay line and transmitted from a predetermined tap thereof to a first input of an EXCLUSIVE OR gate. The second input of the EXCLUSIVE OR gate receives the undelayed input clock signal and generates the output clock signal in response to performing an EXCLUSIVE OR operation on the delayed and undelayed signals. The duty cycle of the output signal is monitored via a comparator in combination with logic circuitry. The output of the comparator is connected to the up/down input of a digital counter which is clocked once for each cycle of the input signal, and generates a digital count value in response thereto. In the event that the monitored duty cycle is less than fifty percent, the comparator generates an up count signal for incrementing the digital counter.