Abstract: The first logic wafer is attached to a supporting wafer, which adds sufficient depth to this bonded structure such that the first logic wafer may be thinned during the manufacturing process. The first logic wafer is thinned such that the through silicon vias may be etched in the substrate of the first logic wafer so as to provide adequate connectivity to a second logic wafer, which is bonded to the first logic wafer. The second logic wafer adds sufficient depth to this bonded structure to allow the supporting wafer to then be thinned to enable through silicon vias to be added to the supporting wafer so as to provide appropriate connectivity for the entire stacked structure. The thinned supporting wafer is retained in the finished stacked wafer structure and may comprise additional components (e.g. capacitors) supporting the operation of the processing circuitry in the logic wafers.

Abstract: A substrate and a method for manufacturing the substrate. The substrate is suitable for mounting at least one semiconductor die onto a printed circuit board. The substrate comprises two opposing stacks, with each stack comprising alternating layers of copper and electrically insulating film. The film and the copper have different co-efficients of thermal expansion, allowing the warpage behaviour of the substrate to be controlled by providing the substrate with different film thicknesses between the opposing stacks.

Abstract: In an embodiment a method includes forming a dielectric membrane on a semiconductor substrate comprising a bulk-etched cavity portion, forming a heater within or over the dielectric membrane, forming a material for sensing a gas on a side of the dielectric membrane, forming a support structure near the material, wherein the support structure comprises an inorganic material and forming a gas permeable region coupled to the support structure in order to protect the material.

Abstract: A gas sensor with a gas permeable region is disclosed. In an embodiment a gas sensor includes a dielectric membrane formed on a semiconductor substrate having a cavity portion, a heater located within or over the dielectric membrane, a material for sensing a gas, wherein the material is located on one side of the dielectric membrane, a support structure located near the material, a gas permeable membrane coupled to the support structure so as to protect the material, wherein the semiconductor substrate forms the support structure.

Abstract: We disclose herein an electronic device comprising: a state machine for receiving an output signal from a sensor; a comparator operatively coupled with the state machine; and a first processor operatively coupled with the comparator. The state machine is configured to receive the output signal from the at least one sensor to obtain sensor measurement data and configured to pass the obtained sensor measurement data to the comparator. The comparator is configured to process the obtained sensor measurement data into first processed sensor data, and configured to compare the first processed sensor data with a first predetermined threshold limit. The comparator is configured to inform the first processor about the obtained sensor measurement data if the first processed sensor data exceed the first predetermined threshold limit.

Abstract: We disclose herein a method for heating a gas sensing material formulation on a microhotplate which comprises: a dielectric membrane formed on a semiconductor substrate comprising an etched portion; and the gas sensing material formulation being located on one side of the dielectric membrane. The method comprising: selectively heating the gas sensing material formulation using an infra-red (IR) heater located over the substrate, and controllably cooling the semiconductor substrate using a cooling baseplate provided under the substrate and using an insulating medium located between the substrate and the cooling base plate so that a gas sensing structure is formed on said one side of the dielectric membrane from the gas sensing material formulation.

Abstract: A gas sensing device comprising a substrate comprising an etched cavity portion and a substrate portion; a dielectric layer disposed on the substrate. The dielectric layer comprises a dielectric membrane. The dielectric membrane is adjacent to the etched cavity portion of the substrate. The dielectric membrane comprises an etched recess portion, a heater located within the dielectric layer, and a material for sensing a gas. The material for sensing a gas is located within the etched recess portion of the dielectric membrane.

Abstract: We disclose herein a method for testing a batch of environmental sensors to determine the fitness for purpose of the batch of environmental sensors, the method comprising: performing a plurality of electrical test sequences to the sensor inputs of the batch of environmental sensors to measure electrical responses of the sensor outputs of the batch of environmental sensors; correlating the measured electrical responses from the batch of environmental sensors to predetermined environmental parametric ranges of at least one environmental sensor so as to define correlated electrical test limits; and determining the fitness for purpose of the batch of environmental sensors if the measured electrical responses are within the correlated electrical test limits.

Abstract: We disclose herein an environmental sensor system comprising an environmental sensor comprising a first heater and a second heater in which the first heater is configured to consume a lower power compared to the second heater. The system also comprises a controller coupled with the environmental sensor. The controller is configured to detect if a measured value of a targeted environmental parameter is present. The controller is configured to switch on at least one of the first and second heaters based on the presence and/or result of the measured value of the targeted environmental parameter.

Abstract: We disclose herein a method for heating a gas sensing material formulation on a microhotplate which comprises: a dielectric membrane formed on a semiconductor substrate comprising an etched portion; and the gas sensing material formulation being located on one side of the dielectric membrane. The method comprising: selectively heating the gas sensing material formulation using an infra-red (IR) heater located over the substrate, and controllably cooling the semiconductor substrate using a cooling baseplate provided under the substrate and using an insulating medium located between the substrate and the cooling base plate so that a gas sensing structure is formed on said one side of the dielectric membrane from the gas sensing material formulation.

Abstract: Disclosed herein is a gas sensing device comprising a dielectric membrane formed on a semiconductor substrate comprising a bulk-etched cavity portion, a heater located within or over the dielectric membrane, a material for sensing a gas which is located on one side of the membrane, a support structure located near the material, and a gas permeable region coupled to the support structure so as to protect the material.

Abstract: We disclose herein an environmental sensor system comprising an environmental sensor comprising a first heater and a second heater in which the first heater is configured to consume a lower power compared to the second heater. The system also comprises a controller coupled with the environmental sensor. The controller is configured to detect if a measured value of a targeted environmental parameter is present. The controller is configured to switch on at least one of the first and second heaters based on the presence and/or result of the measured value of the targeted environmental parameter.

Abstract: We disclose herein a method for testing a batch of environmental sensors to determine the fitness for purpose of the batch of environmental sensors, the method comprising: performing a plurality of electrical test sequences to the sensor inputs of the batch of environmental sensors to measure electrical responses of the sensor outputs of the batch of environmental sensors; correlating the measured electrical responses from the batch of environmental sensors to predetermined environmental parametric ranges of at least one environmental sensor so as to define correlated electrical test limits; and determining the fitness for purpose of the batch of environmental sensors if the measured electrical responses are within the correlated electrical test limits.

Abstract: We disclose herein an electronic device comprising: a state machine for receiving an output signal from a sensor; a comparator operatively coupled with the state machine; and a first processor operatively coupled with the comparator. The state machine is configured to receive the output signal from the at least one sensor to obtain sensor measurement data and configured to pass the obtained sensor measurement data to the comparator. The comparator is configured to process the obtained sensor measurement data into first processed sensor data, and configured to compare the first processed sensor data with a first predetermined threshold limit. The comparator is configured to inform the first processor about the obtained sensor measurement data if the first processed sensor data exceed the first predetermined threshold limit.

Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, and buffer layers having a Young's Modulus of 2.5 GPa or less.

Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, and buffer layers having a Young's Modulus of 2.5 GPa or less.

Abstract: A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, said buffer layers having a Young's Modulus of 2.5GPa or less.

Abstract: An electrical interconnect for connecting an IC chip to a PCB, the electrical interconnect comprising a plurality of connection elements for connection to the PCB attached to a first surface of the electrical interconnect, wherein the amount of thermal and/or mechanical stress that each solder element connection can take before failing is improved.

Abstract: Methods of fabricating a QFN with wettable flank are described. In an embodiment, a leadframe is used which comprises regions of reduced thickness dam bar which extend across an edge of a kerf width and the QFN are formed using film assisted molding with a shaped mold chase that comprises raised portions which correspond in shape and position to the one or more regions of reduced thickness in the leadframe. The shaped mold chase prevents mold compound from filling recesses under the regions of reduced thickness of leadframe and once diced, each QFN has an edge structure which comprises a small step, into which solder will wet where there are exposed plated leads.

Abstract: A method for forming a stacked integrated circuit package of primary dies on a carrier die, includes forming electrically conductive pillars at connection pads defined on an active face of a carrier wafer incorporating carrier integrated circuits, the electrically conductive pillars providing electrical connections to said carrier integrated circuits; attaching primary dies to the active face of the carrier wafer, each supporting electrically conductive pillars at connection pads defined on an active face of the primary die; encapsulating the active face of the carrier wafer and the primary dies attached thereto in an insulating material; producing a wafer package by removing a thickness of the insulating layer sufficient to expose the electrically conductive pillars; and singulating the carrier wafer to form stacked integrated circuit packages, each package comprising at least one primary die on a carrier die.