Patents by Inventor Simon JORET

Simon JORET has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for determining the phase difference between a first clock signal received by a first electronic component and a second clock signal received by a second electronic component
    Patent number: 12425011
    Abstract: The invention relates to a method for determining the phase difference between a first clock signal (CK1) received by a first electronic component (CE1) and a second clock signal (CK2) received by a second electronic component (CE2), comprising the steps of: S10) transmitting a first calibration signal (S12); S20) measuring a first delay (T1); S30) transmitting a second calibration signal (S21); S40) measuring a second delay (T2); S50) measuring the number (n) of clock pulses between the transmission of the first calibration signal (S12) and the active edge of the first clock signal (CK1) consecutive to the active edge of the second calibration signal (S21); S60) determining the phase difference depending on the parity of the number (n) of clock pulses.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: September 23, 2025
    Assignee: Teledyne e2v Semiconductors SAS
    Inventors: Simon Joret, Quentin Beraud-Sudreau, Rémi Laube, St éphane Breysse, Matthieu Martin, Julien Cochard
  • METHOD FOR DETERMINING THE PHASE DIFFERENCE BETWEEN A FIRST CLOCK SIGNAL RECEIVED BY A FIRST ELECTRONIC COMPONENT AND A SECOND CLOCK SIGNAL RECEIVED BY A SECOND ELECTRONIC COMPONENT
    Publication number: 20240120909
    Abstract: The invention relates to a method for determining the phase difference between a first clock signal (CK1) received by a first electronic component (CE1) and a second clock signal (CK2) received by a second electronic component (CE2), comprising the steps of: S10) transmitting a first calibration signal (S12); S20) measuring a first delay (T1); S30) transmitting a second calibration signal (S21); S40) measuring a second delay (T2); S50) measuring the number (n) of clock pulses between the transmission of the first calibration signal (S12) and the active edge of the first clock signal (CK1) consecutive to the active edge of the second calibration signal (S21); S60) determining the phase difference depending on the parity of the number (n) of clock pulses.
    Type: Application
    Filed: September 13, 2023
    Publication date: April 11, 2024
    Inventors: Simon JORET, Quentin BERAUD-SUDREAU, Rémi LAUBE, Stéphane BREYSSE, Matthieu MARTIN, Julien COCHARD