Abstract: To enhance the performance of computing arithmetic operations, where the operations can utilize the matrix multiplication process available on processing units. The matrix multiplication process can be implemented as software, a hardware unit that is part of the processing unit, or a combination thereof. Utilizing the matrix multiplication process can utilize available processing bandwidth that would ordinarily not be used for the arithmetic operation. The process can decompose the arithmetic operation to a modular multiplication operation. The modular multiplication operation can be transformed to a redundant representation. The redundant representation can be mapped to the matrix multiplication process. The result can be computed and returned to the calling thread. In some aspects, the result can be a recombination of partial redundant representations that are offset to provide the appropriate place holder values.