Abstract: A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design. The compatibility of the second area may be identified based on fabric tile signatures of the first area and the second area.

Abstract: A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design. The compatibility of the second area may be identified based on fabric tile signatures of the first area and the second area.

Abstract: A logic block can be relocated without recompilation from a first area to a second area on a field-programmable gate array (FPGA) if the pattern of fabric tiles in the second area is the same as the pattern of fabric tiles in the first area, and if the two areas have the same dimensions. The design system runs synthesis, placement, and routing on a partition of a design at a first location, exports that partition to a persistent on-disk database, imports one or multiple copies of the partition into a larger design, and moves one or more of the copies from the first area to a target area in the larger design.

Abstract: A method of display unconversion wherein each output field line is interpolated from at least three input field lines from each of at least three input fields. By increasing the field rate by 1.5 (instead of simple field doubling) and by increasing the line rate by 1.5 (instead of simple line doubling) a substantial increase in picture quality can be achieved while maintaining data flow rates within manageable limits.