Abstract: This invention relates to a method of building a hybrid quantum-classical computing network, comprising: a first step of transformation of an application composed of services into a Petri net including both Petri places (8, 9) and Petri transitions (81, 82, 91-94) between said Petri places (8, 9), any said Petri place (8, 9) corresponding to: either a first type building block corresponding to any quantum processing unit (8) which processes a job into a result, or a second type building block corresponding to any plugin unit (9), which converts a job into another job and/or a result into another result, any Petri transition (81, 82, 91-94) corresponding to any link between two building blocks (8, 9), all said links (81, 82, 91-94) being formatted so as to make any building block (8, 9) interchangeable, a second step of transformation of said Petri net into a hybrid quantum-classical computing network, replacing any building block by its corresponding unit (8, 9), interconnecting all said corresponding units (

Abstract: Method for implementing a quantum circuit comprising a plurality of qubits as well as operators executed on said qubits, said operators comprising a sequence of ? 4 Pauli rotation gates, a surface code layout comprising an arrangement of said quantum circuit on a quantum chip, the arrangement comprising at least a tree with a plurality of subtrees, at each rotation gate corresponding a subtree of the tree, the method comprising: generating iteratively a directed acyclic graph of said quantum circuit, a front layer of the DAG being a set of rotations that can be effectively implemented at each iteration, and selecting in said front layer of the DAG a subset, called selected subset, of said set of rotations among subsets, called non intersecting subsets, in which the subtrees are arranged not to intersect.

Abstract: Method for implementing a graph (G) comprising a plurality of vertices (V) and links (E) between the vertices, a set (R) being a collection of subsets (Ri) of said a given number of vertices (Rik) comprising: in said set (R), selecting subsets (Ri, Rj), called pre-selected subsets, such that a tree (Ti, Tj) is associated respectively to said tree (Ti, Tj), said associated trees (Ti, Tj) being pairwise disjoint; comparing the number of vertices (Rik) associated to each of the pre-selected subset, among the pre-selected subsets, choosing the subset for which the number of vertices is the highest

Abstract: Method for implementing a graph (G) comprising a plurality of vertices (V) and links (E) between the vertices, a set (R) being a collection of subsets (Ri) of said a given number of vertices (Rik) comprising: in said set (R), selecting subsets (Ri, Rj), called pre-selected subsets, such that a tree (Ti, Tj) is associated respectively to said subset (Ri, Rj), said associated trees (Ti, Tj) being pairwise disjoint and constructing (301) each tree (Ti); associating a weight to each said tree (Ti); choosing the subset for which the tree (Ti) has the highest weight.

Abstract: A method for compiling a quantum circuit on a trapped-ion quantum processor includes: obtaining a quantum circuit containing a first predetermined category of two-qubit quantum gates, and/or one-qubit quantum gates; a separation of the quantum circuit into local layers, and entangling layers; compiling the local layers; compiling the entangling layers, separate from the step of compiling the local layers, transforming the quantum gates of those entangling layers so that they contain only collective or entangling N-qubit quantum gates of a third predetermined category, one-qubit quantum gates of a fourth predetermined category; and a step of grouping together the compiled local layers and the compiled entangling layers into a compiled quantum circuit.

Abstract: A method for the development of a compilation process for a quantum circuit on a quantum processor, includes an implementation step of the compilation method including an iteration loop successively including: a step of simulation of a given implementation of the logical qubits on the physical qubits of the quantum processor; a step of detecting, in the quantum circuit, ineffective quantum gate(s); a step of estimating the number of quantum swap gates to be inserted into the quantum circuit so that all of the quantum gates of the quantum circuit are effective; and a retroaction step, by way of a simulated annealing, involving a new step of simulation, until attaining, whereupon all the quantum gates are effective: either a minimum threshold of the number of estimated quantum value swap gates between two physical qubits, or a maximum threshold of iterations in the loop.

Abstract: The present disclosure relates to a computing system for executing hybrid programs, said computing system comprising: hardware resources comprising quantum computing resources and classical computing resources, said quantum computing resources comprising one or more quantum computers; software resources to be executed on the hardware resources; wherein the software resources comprise a plurality of processing modules comprising interfaces of two possible types referred to as upstream interface and downstream interface, wherein said plurality of processing modules comprises: at least one quantum processing module for each quantum computer, wherein each quantum processing module comprises an upstream interface; a plurality of plugin modules, wherein each plugin module comprises both an upstream interface and a downstream interface; wherein a hybrid program is built by connecting at least one plugin module and one quantum processing module.

Abstract: The present disclosure relates to a computing system comprising a classical computer, an analog quantum computer and a digital quantum computer, said computing system comprising: a digital quantum processing, DQP, module comprising an input interface for receiving a quantum circuit to be executed by the digital quantum computer; an analog quantum processing, AQP, module comprising an input interface for receiving a temporal schedule to be executed by the analog quantum computer; a digital to analog converting, DAC, module comprising an input interface for receiving a quantum circuit and an output interface for outputting a temporal schedule; wherein a same format is used on the input interfaces of both the DQP module and the DAC module, and a same format is used on both the output interface of the DAC module and the input interface of the AQP module.

Abstract: This invention relates to a method of building a hybrid quantum-classical computing network, comprising: a first step of transformation of an application composed of services into a Petri net including both Petri places (8, 9) and Petri transitions (81, 82, 91-94) between said Petri places (8, 9), any said Petri place (8, 9) corresponding to: either a first type building block corresponding to any quantum processing unit (8) which processes a job into a result, or a second type building block corresponding to any plugin unit (9), which converts a job into another job and/or a result into another result, any Petri transition (81, 82, 91-94) corresponding to any link between two building blocks (8, 9), all said links (81, 82, 91-94) being formatted so as to make any building block (8, 9) interchangeable, a second step of transformation of said Petri net into a hybrid quantum-classical computing network, replacing any building block by its corresponding unit (8, 9), interconnecting all said corresponding units (

Abstract: The present disclosure relates to a compiling method (50) for converting an input quantum circuit into an output quantum circuit compliant with predetermined constraints of a quantum computer, said input quantum circuit being composed of quantum gates to be applied to a set of qubits, said quantum gates arranged successively in an execution order, wherein said method comprises, for each quantum gate of the input quantum circuit processed according to the execution order: if the processed quantum gate corresponds to an operator of a set of synthesizable operators: (S53) update the synthesizable accumulated operator to include the operator corresponding to the quantum gate, otherwise: a) (S54) synthesize a partial quantum sub-circuit partially implementing the current synthesizable accumulated operator and modify accordingly the synthesizable accumulated operator, and b) (S55) append the partial quantum sub-circuit to the output quantum circuit.

Abstract: A method for synthesizing a product of Pauli rotations, wherein said product of Pauli rotations comprises at least two different types of X, Y and/or Z n-qubits Pauli rotations and identities, where the method comprises: providing a table of p number of rows and m number of columns, where p is a number of qubits and m a number of rotations, each column describing one Pauli rotation and each row describing a qubit, the method performing iteratively, until the table is empty: a step of simulating conjugations of at least one pair of rows by simulating the insertion of a predetermined type of quantum gates on their respective qubit in order to bring one of the X, Y or Z entry of at least one column to an identity entry, for each simulation, a step of counting the number of identity entries that appeared, a step of associating a score to each simulation, where the higher score corresponds to the simulation bringing the most identity entries in the associated column, and a step of performing one conjugation,

Abstract: Examples include quantum computing compiling methods comprising considering a threshold corresponding to a maximum number of qubits available for processing in any one subsystem of a plurality of interconnected qubit subsystems and identifying a total number of qubits submitted to a specific quantum circuit, the total number of qubits exceeding the threshold. The methods comprise compiling a first section of the specific quantum circuit on a first subsystem by successively selecting quantum gates. If a selected quantum gate is to be applied to qubits assigned to different subsystems, the passing of a qubit from the first subsystem to a second subsystem through a junction connecting the first subsystem to the second subsystem is coded, and the second section of the specific quantum circuit is compiled on the second subsystem.

Abstract: Examples relate to a quantum computing compiling method that includes ordering quantum gates of a nearest neighbor quantum circuit in function of dependencies between the quantum gates to obtain a quantum gates hierarchical order. The hierarchical order includes a succession of front lines comprising multiple respective quantum gates of the nearest neighbor quantum circuit. The method includes successively selecting, for each front line, and following the hierarchical order, a shuttling for each respective quantum gate of the front line. The shuttling selection is, for each front line, based on a predefined constraint.

Abstract: A method for generalizing an algorithm configured to synthesize a diagonal product of Pauli rotations to synthesize a product of Pauli rotations comprising X, Y and Z rotations, the method comprising: Providing a table of p number of rows and m number of columns, where p is a number of qubits and m a number of rotations in the quantum circuit, and where the table comprises X, Y, Z or I entry corresponding to the respective rotations of the qbits; Determining a pivot row, and recursively, until all rotations of the product of Pauli rotations are 1-qubit rotations: Determine a target row, Conjugate the target row with the pivot row by insertion of predetermined quantum gates on the qubits corresponding to the target row and/or pivot row by calling, at each recursive call, entries of the same type of the pivot row and by always calling first the identity entry.

Abstract: The present disclosure relates to a compiling method (50) for converting an input quantum circuit into an output quantum circuit compliant with predetermined constraints of a quantum computer, said input quantum circuit being composed of quantum gates to be applied to a set of qubits, said quantum gates arranged successively in an execution order, wherein said method comprises, for each quantum gate of the input quantum circuit processed according to the execution order: if the processed quantum gate corresponds to an operator of a set of synthesizable operators: (S53) update the synthesizable accumulated operator to include the operator corresponding to the quantum gate, otherwise: a) (S54) synthesize a partial quantum sub-circuit partially implementing the current synthesizable accumulated operator and modify accordingly the synthesizable accumulated operator, and b) (S55) append the partial quantum sub-circuit to the output quantum circuit.

Abstract: Examples include quantum computing compiling methods comprising considering a threshold corresponding to a maximum number of qubits available for processing in any one subsystem of a plurality of interconnected qubit subsystems and identifying a total number of qubits submitted to a specific quantum circuit, the total number of qubits exceeding the threshold. The methods comprise compiling a first section of the specific quantum circuit on a first subsystem by successively selecting quantum gates. If a selected quantum gate is to be applied to qubits assigned to different subsystems, the passing of a qubit from the first subsystem to a second subsystem through a junction connecting the first subsystem to the second subsystem is coded, and the second section of the specific quantum circuit is compiled on the second subsystem.

Abstract: A method for compiling a quantum circuit on a trapped-ion quantum processor includes: obtaining a quantum circuit containing only a first predetermined category of two-qubit quantum gates, and/or one-qubit quantum gates; a step of compiling the quantum gates so that they only contain collective or entangling N-qubit quantum gates of a third predetermined category, one-qubit quantum gates of a fourth predetermined category, and so that all or at least some of those collective or entangling quantum gates simultaneously apply to at least three qubits, advantageously simultaneously apply to the majority of qubits, and even more advantageously simultaneously apply to all the qubits; and a step of grouping together the compiled quantum gates in a compiled quantum circuit.

Abstract: Examples relate to a quantum computing compiling method that includes ordering quantum gates of a nearest neighbor quantum circuit in function of dependencies between the quantum gates to obtain a quantum gates hierarchical order. The hierarchical order includes a succession of front lines comprising multiple respective quantum gates of the nearest neighbor quantum circuit. The method includes successively selecting, for each front line, and following the hierarchical order, a shuttling for each respective quantum gate of the front line. The shuttling selection is, for each front line, based on a predefined constraint.

Abstract: A method for developing a method for compiling a quantum circuit on a quantum processor, comprising: a selection step: of a quantum circuit, of a quantum processor whereupon to compile the quantum circuit, of a set of quantum gates that can be executed on the selected quantum processor, of a metric, a meta-heuristic, a step of division of the selected quantum circuit into quantum sub-circuits, a first step of re-writing of the quantum sub-circuits comprising quantum gates that cannot be executed by the selected quantum processor to comprise only quantum gates that can be executed by the selected quantum processor, a second step of re-writing of the quantum sub-circuits, by the selected meta-heuristic, to obtain quantum sub-circuits comprising quantum gates that can be executed by the selected quantum processor, improving the selected metric, a step of regrouping of the quantum sub-circuits in a quantum circuit compilable by the selected quantum processor.

Abstract: Disclosed is a method for optimizing a quantum circuit of an ordered series of quantum gates, applied to an initial layout of qubit values, consisting in inserting a set of local SWAP gates so that all gates of the circuit are local, the method including: for each gate, if it is not local, inserting a set of local SWAP gates; determining the set of permutations, each consisting of a succession of swaps of qubit values along shortest paths between positions of qubits associated with the gate; and choosing, from the permutations, a permutation that minimizes a cost representing the number of swaps necessary to make the gates of a sequence within the series, of substantially smaller size, local; re-establishing the initial layout by establishing a tree covering a graph representative of the layout of the qubits of the circuit, and by swapping qubit values along paths of the tree.