Abstract: A method for hiding texture latency in a multi-thread virtual pipeline (MVP) processor including the steps of: allowing the MVP processor to start running a main rendering program; segmenting registers of various MVP kernel instances in the MVP processor according to the length set, acquiring a plurality of register sets with the same length, binding the register sets to chipsets of the processor at the beginning of the running of the kernel instance; allowing a shader thread to give up a processing time slot occupied by the shader thread after sending a texture detail request, and setting a Program Counter (PC) value in the case of return; and returning texture detail and allowing the shader thread to restart running.

Abstract: The present invention relates to a thread control method of a multi-thread virtual pipeline (MVP) processor, which comprises the following steps: allocating directly and sequentially threads in a central processing unit (CPU) thread operation queue to multi-path parallel hardware thread time slots of the MVP processor for operation; allowing an operating thread to generate hardware thread call instructions corresponding thereto to a hardware thread management unit; allowing the hardware thread management unit to enable the call instructions of ithread threads to form a program queue according to receiving time, and calling and preparing the hardware threads; and allowing the hardware threads to operate sequentially in idle multi-path parallel hardware thread time slots of the MVP processor according to the sequence of the hardware threads in the queue of the hardware thread management unit. The present invention also relates to a processor.

Abstract: The invention relates to a method for hiding texture latency in an MVP processor, which comprises the following steps of: allowing the MVP processor to start running a main rendering program; segmenting registers of various MVP kernel instances in the MVP processor according to the length set, acquiring a plurality of register sets with same length, and binding the register sets to the dies at the beginning of the running of the kernel instance; allowing a shader thread to give up a processing time slot occupied by the shader thread after sending a texture detail request, and setting a PC (Program Counter) value in the case of return; and returning texture detail and allowing the shader thread to restart running. The invention also relates to a method for managing registers of grahic processing threads in the MVP processor.

Abstract: A multithreaded processor and method for realizing the functions of a central processing unit and a graphics processing unit, including a graphics fixed function processing module for performing a fixed function processing on data during a graphics processing, a multithreaded parallel central processing module for realizing a central processing function and a programmable processing function of a graphics processing through a uniform thread scheduling and exchanging the graphics data subjected to the programmable processing with the graphics fixed function processing module through a storage module, and a storage module for providing a uniform storage space for the graphics fixed function processing module and the multithreaded parallel central processing module to store, buffer and/or exchange data. The multithreaded processor and method for realizing the functions of a central processing unit and a graphics processing unit allow load balancing among multiple thread processing engines.

Abstract: A stream data processing method is provided, which includes the steps as follows: obtaining from data a program pointer indicating a task to which the pointer belongs, and configures a thread processing engine according to the program pointer; processing simultaneously the data of the different durations of the task or the data of different tasks by a plurality of thread engines; decides whether there is data still not processed, and if yes, returns to the first step; and if no, exits this data processing. A processor for processing a stream data is also provided.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: A parallel processor and a method for concurrently processing threads in the parallel processor are disclosed. The parallel processor comprises: a plurality of thread processing engines for processing threads distributed to the thread processing engines, and the plurality of thread processing engines being connected in parallel; a thread management unit for obtaining, judging the statuses of the plurality of thread processing engines, and distributing the threads in a waiting queue among the plurality of thread processing engines.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: Methods and apparatuses for processing a Configurable Single-Instruction-Multiple-Data (CSIMD) instruction are disclosed. In the method, a lookup table (LUT) storing information is provided to support random access of memory locations associated with a plurality of processing elements (PEs) and to perform instruction variances by the PEs. A CSIMD instruction is received, comprising a command and an index to the lookup table (LUT), to be executed by the PEs. The command of the received CSIMD instruction is executed in parallel differently by the PEs using the LUT index to randomly access the memory locations.

Abstract: Methods and apparatuses for processing a Configurable Single-Instruction-Multiple-Data (CSIMD) instruction are disclosed. In the method, a lookup table (LUT) storing information is provided to support random access of memory locations associated with a plurality of processing elements (PEs) and to perform instruction variances by the PEs. A CSIMD instruction is received, comprising a command and an index to the lookup table (LUT), to be executed by the PEs. The command of the received CSIMD instruction is executed in parallel differently by the PEs using the LUT index to randomly access the memory locations.

Abstract: Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: A system and method are provided for a hardware implementation of a blending technique during graphics processing in a graphics pipeline. During processing in the pipeline, a plurality of matrices and a plurality of weight values are received. Also received is vertex data to be processed. A sum of a plurality of products may then be calculated by the multiplication of the vertex data, one of the matrices, and at least one of the weights.

Abstract: A graphics pipeline system and method are provided for graphics processing. Such system includes a transform module positioned on a single semiconductor platform for transforming graphics data from object space to screen space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for lighting the graphics data. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the graphics data.

Abstract: A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

Abstract: A graphics pipeline system and associated method are provided for graphics processing. Such system includes a transform module adapted for receiving graphics data. The transform module serves to transform the graphics data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for lighting the graphics data. During use, the graphics pipeline system is capable of carrying out a fog and blending operation.

Abstract: A graphics pipeline system with an integrated masking operation is provided. Included is a transform module adapted for being coupled to a buffer to receive graphics data therefrom. Such transform module is positioned on a single semiconductor platform for transforming the graphics data from a first space to a second space. Also included is a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module. The lighting modules serves for performing lighting operations on the graphics data received from the transform module. In use, a masking operation is further performed on the single semiconductor platform.

Abstract: A method, apparatus and article of manufacture are provided for a transform system for graphics processing as a computer system or on a single integrated circuit. Included is an input buffer adapted for being coupled to a vertex attribute buffer for receiving vertex data therefrom. A multiplication logic unit has a first input coupled to an output of the input buffer. Also provided is an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit. Coupled to an output of the arithmetic logic unit is an input of a register unit. An inverse logic unit is provided including an input coupled to the output of the arithmetic logic unit or the register unit for performing an inverse or an inverse square root operation. Further included is a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit. In use, the conversion module serves to convert scalar vertex data to vector vertex data.