Abstract: The present disclosure describes an integrated circuit device that includes a digital signal processing (DSP) block. The DSP block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Also, the first plurality of inputs, the second plurality of inputs, or both are derived from higher precision values. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

Abstract: The present disclosure describes an integrated circuit device that includes a digital signal processing (DSP) block. The DSP block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Also, the first plurality of inputs, the second plurality of inputs, or both are derived from higher precision values. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

Abstract: The present embodiments relate to an address generator circuit for addressing a storage circuit. The address generator circuit may generate address signals for read and write access operations at the storage circuit. The write access operation may store a two-dimensional array in the storage circuit and the read access operation may retrieve a transpose of the two-dimensional array from the storage circuit. The address generator circuit may include a status flag generation circuit that generates status flag signals, a modulo adder circuit that receives first and second signals and computes a modulo adder output signal, and an address processing circuit. The address processing circuit may receive the modulo adder output signal from the modulo adder circuit and the plurality of status flag signals from the status flag generation circuit and provide the first and second signals to the modulo adder circuit.

Abstract: Circuitry that accepts a data input and an enable input, and generates an output sum based on the data input includes an input stage circuit that includes an input register. The input register accepts the enable input. The circuitry further includes a systolic register operatively connected to the input stage circuit, and the systolic register is operated without any enable connection. The circuitry further includes a multiplier connected to the systolic register, which is configured to generate a product value. The circuitry further includes an output stage circuit that includes an adder that calculates the output sum based least in part on the product value.

Abstract: Circuitry that accepts a data input and an enable input, and generates an output sum based on the data input includes an input stage circuit that includes an input register. The input register accepts the enable input. The circuitry further includes a systolic register operatively connected to the input stage circuit, and the systolic register is operated without any enable connection. The circuitry further includes a multiplier connected to the systolic register, which is configured to generate a product value. The circuitry further includes an output stage circuit that includes an adder that calculates the output sum based least in part on the product value.