Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

Abstract: Provided are anti-CD8 antibodies that bind human CD8 and do not stimulate or inhibit the activation of CD8+ T cells. Also provided are nucleic acids encoding such anti-CD8 antibodies, vectors comprising such nucleic acids, host cells comprising same, and methods of making such anti-CD8 antibodies. Also provided are anti-CD8 antibodies conjugated to a detectable label. Provided are methods of using such anti-CD8 antibodies to detect CD8+ T cells in a subject, monitor disease progress in a subject having cancer, and monitor treatment progress in a subject having cancer.

Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.

Abstract: Provided are anti-CD8 antibodies that bind human CD8 and do not stimulate or inhibit the activation of CD8+ T cells. Also provided are nucleic acids encoding such anti-CD8 antibodies, vectors comprising such nucleic acids, host cells comprising same, and methods of making such anti-CD8 antibodies. Also provided are anti-CD8 antibodies conjugated to a detectable label. Provided are methods of using such anti-CD8 antibodies to detect CD8+ T cells in a subject, monitor disease progress in a subject having cancer, and monitor treatment progress in a subject having cancer.

Abstract: Media processing systems and techniques are described. A media processing system receives image data that represents an environment captured by an image sensor. The media processing system receives an indication of an object in the environment that is represented in the image data. The media processing system divides the image data into regions, including a first region and a second region. The object is represented in one of the plurality of regions. The media processing system modifies the image data to obscure the first region without obscuring the second region based on the object being represented in the one of the plurality of regions. The media processing system outputs the image data after modifying the image data. In some examples, the object is depicted in the first region and not the second region. In some examples, the object is depicted in the second region and not the first region.

Abstract: The present invention relates to deuterated and optionally detectably labeled compounds of formula (I) and formula (V): and salts thereof, wherein R1, R2, A, and X10-X19 have any of the values defined in the specification. Also included are pharmaceutical compositions comprising such compounds and salts, and methods of using such compounds and salts as imaging agents.

Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

Abstract: Provided are CD8 binding agents comprising a VHH domain that specifically binds human CD8. Also provided are nucleic acids encoding such CD8 binding agents, vectors comprising such nucleic acids, host cells comprising same, and methods of making such CD8 binding agents. Also provided are CD8 binding agents having the VHH domain conjugated to a detectable label. Provided are methods of using such CD8 binding agents to detect CD8+ T cells, monitor disease progress, and monitor treatment progress in a subject having cancer, autoimmune disease or condition, transplant rejection or graft-versus-host disease.

Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.

Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.

Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.

Abstract: In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving: (i) a first set of votes from a first client of a system, and (ii) a second set of votes from a second client of the system, wherein the first set of votes indicate a first desired set of operational parameters for controlling a plurality of physical resources in the system, wherein the second set of votes indicate a second desired set of operational parameters for controlling the plurality of physical resources, and wherein the plurality of physical resources are shared by the first client and the second client.

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

Abstract: In some aspects, the present disclosure provides a method for bandgap voting. In some configurations, the method includes receiving: (i) a first set of votes from a first client of a system, and (ii) a second set of votes from a second client of the system, wherein the first set of votes indicate a first desired set of operational parameters for controlling a plurality of physical resources in the system, wherein the second set of votes indicate a second desired set of operational parameters for controlling the plurality of physical resources, and wherein the plurality of physical resources are shared by the first client and the second client.

Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.