Abstract: A waveguide delay-based equalization (WDEQ) system is described. The WDEQ system provides a delay in waveguides of the system and electrical signal summing in a differential transimpedance amplifier (TIA) which increases the performance (e.g., bandwidth, etc.) of the optical receiver. The WDEQ system includes an optoelectronic circuit with a directional coupler, a first photodetector, at least two transistors connected to the first photodetector, an optical delay, and a differential transimpedance amplifier (TIA).

Abstract: A differential transimpedance amplifier (DTIA) includes a first input, a second input, a first output, and a second output. The DTIA also includes a first inverter and a second inverter connected in series to the first input. The DTIA further includes a third inverter and a fourth inverter connected in series to the second input. The first inverter and the fourth inverter receive a first supply voltage from a first voltage regulator. The second inverter and the third inverter receive a second supply voltage from a second voltage regulator. The first supply voltage changes (i) based on a difference between voltages on the first output and the second output and (ii) while the second supply voltage remains fixed.

Abstract: Automatic protection switching is implemented by channel devices in a data communication system node. Each channel devices includes input and output ports, a data receive port, a data send port, and a signal routing arrangement controlled by a processor element. The signal routing arrangement routes data between the channel devices such that, in the event of a channel failure, one channel device functions as a protection channel device. In a normal operating mode, each channel device routes data from its data receive port to its data send port, and routes data from its input port to its output port. In a protection mode, the protection channel device (and the protected channel device) routes data from its data receive port to its output port, and routes data from its input port to its data send port, while the remaining working channel devices function in the normal operating mode.

Abstract: A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.

Abstract: A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.