Patents by Inventor Simon Sabato

Simon Sabato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9647688
    Abstract: A method of encoding a data word in a physical coding sublayer before serial transmission is provided, where data words comprising data bits are received, and the data words encoded using one or more 8B/10B encodings to generate 8B/10B transmission characters. ECC check bits are then generated, and the transmission characters and ECC check bits DC balanced prior to shuffling the bits together to form an encoded word to be transmitted. A receiver may decode by implementing a decode process with error correction. In some embodiments 26 data bits from two 13-bit word are encoded into a 40-bit encoded word. Bits of two or more encoded words may be interleaved for transmission, or multiple copies of encoded words sent. An integrated circuit serializer/deserializer comprises hardware to perform encoding and/or decoding. A hardware functional verification system may also implement the disclosed encoding/decoding for interconnections between emulation chips.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 9, 2017
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Mitchell G. Poplack, Simon Sabato
  • Patent number: 9379846
    Abstract: In one form a method of encoding a data word for serial transmission is provided, where a data word comprising a plurality of data bits is received, an invert bit having a bit value is appended to the data word, the data bits and invert bit are scrambled, ECC check bits are generated, and the data bits, invert bit, and ECC check bits are shuffled together to form an encoded word to be transmitted from a transmitter. A receiver may decode by implementing a decode process with error correction. The encoded word may also be DC balanced by checking the disparity of the bits to be encoded against a running disparity to invert or not the bits. An integrated circuit serializer/deserializer comprises hardware to perform encoding and/or decoding. A hardware functional verification system may implement the disclosed encoding/decoding for interconnections between emulation chips.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 28, 2016
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Mitchell G. Poplack, Simon Sabato
  • Patent number: 7782885
    Abstract: The disclosure describes queue management based on queue sets. A queue set comprises a group of packets or packet references that are processed as a single entity or unit. For example, when a queue set reaches the head of a queue in which it is stored, the entire queue set including its packets or packet references is passed for scheduling as a single unit. A queue set provides the benefit of a single operation associated with enqueuing and a single operation associated with dequeuing. Since only one operation on a queue is required for the typical case of several packets in a queue set rather than for every packet, the rate of queue operations may be significantly reduced. A queue set has a target data unit size, for example, a roughly equal number of packet bytes represented by each queue set, regardless of the number of packets referenced by a queue set.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: August 24, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: Simon Sabato, Harish R. Devanagondi, You-Wen Yi, Harish P. Belur
  • Patent number: 7668948
    Abstract: A method, apparatus, and system for staggering time zones.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: February 23, 2010
    Assignee: Intel Corporation
    Inventors: Ajith Prasad, Vishram Sarurkar, Simon Sabato
  • Patent number: 7577136
    Abstract: Enhanced switching functionality is achieved by a switching system having of traffic management devices connected with a generic Ethernet switch fabric and an optional flow control device. The traffic management devices use an encapsulated Ethernet frame format to provide an additional of addressing.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: August 18, 2009
    Assignee: Cisco Technology, Inc.
    Inventors: Harish R. Devanagondi, Harish P. Belur, Simon Sabato, Jasper Yeung, You-Wen Yi
  • Patent number: 7107202
    Abstract: A method apparatus for hardware and software co-simulation in ASIC development includes developing hardware and software concurrently and co-simulating the hardware and software therebetween via a network while the hardware and software are being developed. The method and apparatus for hardware and software co-simulation allows the software development and testing of hardware and software to start with the design of hardware so as to reduce an overall system development cycle involving ASICs.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventors: Gopal Hegde, Surendra Rathaur, Miguel Guerrero, Anoop Hegde, Ilango Ganga, Amamath Mutt, Simon Sabato
  • Publication number: 20050071395
    Abstract: A method, apparatus, and system for staggering time zones.
    Type: Application
    Filed: December 31, 2002
    Publication date: March 31, 2005
    Inventors: Ajith Prasad, Vishram Sarurkar, Simon Sabato