Abstract: Embodiments of the present disclosure provide devices, apparatuses, and methods related to FETs with reduced leakage. In some embodiments, devices on a silicon-on-insulator substrate may include a silicon layer; a gate structure at least partially overlaying the silicon layer; and an oxide layer disposed between the partial overlay of the gate structure and the silicon layer, wherein: the oxide layer comprises a first portion and a second portion; the first portion of the oxide layer is thicker than the second portion of the oxide layer; and the first portion of the oxide layer covers at least a portion of a first edge of the silicon layer in the partial overlay.

Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

Abstract: Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

Abstract: An on-chip fuse circuit. The circuit includes a fuse capable of being blown during a programming operation, as well as output logic for determining whether the fuse is blown. A protection circuit is provided for protecting the output logic during programming. An evaluation circuit is provided, for evaluating whether the fuse is blown. The evaluation circuit includes a first current source coupled to the fuse, providing a first predetermined current so as to activate the output logic to read out the condition of the fuse during normal operation, as well as a second current source coupled to the fuse, providing a second predetermined current, substantially less than the first predetermined current, so as to activate the output logic to read out the condition of the fuse during an evaluation mode such that a blown condition is indicated by the output logic only if the resistance of the fuse is substantially greater than that required for the output logic to indicate a blown condition during normal operation.