Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: A back contact integrated photovoltaic cell includes a substrate having a dielectric surface and a patterned metal layer with parallel spaced alternately positive and negative electrode fingers forming an interdigitated two-terminal structure over the dielectric surface of the substrate. A dielectric filler may be in the interstices of separation between adjacent spaced parts of the patterned metal layer. Parallel spaced strips, alternately of p+ doped polysilicon and of n+ doped polysilicon, may top the positive and negative interdigitated electrode fingers, respectively, and form doped p-type active regions and n-type active regions of the integrated photovoltaic cell, spaced and isolated by a strip of undoped or negligibly doped polysilicon. An n? or p? doped or intrinsic semiconducting layer of at least partly crystallized silicon, forming a semiconductor region of thickness adapted to maximize absorption of photonic energy when illuminated by sunlight, may cover the interdigitated active doped regions.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: A back contact integrated photovoltaic cell includes a substrate having a dielectric surface and a patterned metal layer with parallel spaced alternately positive and negative electrode fingers forming an interdigitated two-terminal structure over the dielectric surface of the substrate. A dielectric filler may be in the interstices of separation between adjacent spaced parts of the patterned metal layer. Parallel spaced strips, alternately of p+ doped polysilicon and of n+ doped polysilicon, may top the positive and negative interdigitated electrode fingers, respectively, and form doped p-type active regions and n-type active regions of the integrated photovoltaic cell, spaced and isolated by a strip of undoped or negligibly doped polysilicon. An n? or p? doped or intrinsic semiconducting layer of at least partly crystallized silicon, forming a semiconductor region of thickness adapted to maximize absorption of photonic energy when illuminated by sunlight, may cover the interdigitated active doped regions.

Abstract: A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps: forming on the semiconductor substrate a plurality of trenches, forming a surface layer on the semiconductor substrate in order to close superficially the plurality of trenches forming in the meantime at least a buried cavity in correspondence with the surface-distal end of the trenches.

Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

Abstract: A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps: forming on the semiconductor substrate a plurality of trenches, forming a surface layer on the semiconductor substrate in order to close superficially the plurality of trenches forming in the meantime at least a buried cavity in correspondence with the surface-distal end of the trenches.

Abstract: A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps: forming on the semiconductor substrate a plurality of trenches, forming a surface layer on the semiconductor substrate in order to close superficially the plurality of trenches forming in the meantime at least a buried cavity in correspondence with the surface-distal end of the trenches.

Abstract: A process is presented for realizing buried microchannels in an integrated structure comprising a monocrystalline silicon substrate. The process forms in the substrate at least one trench. A microchannel is obtained starting from a small surface port of the trench by anisotropic etching of the trench. The microchannel is then completely buried in the substrate by growing a microcrystalline structure to enclose the small surface port.

Abstract: A process is presented for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2). The process forms in the substrate (2) at least one trench (4). A microchannel (10) is obtained starting from a small surface port of the trench (4) by anisotropic etching of the trench. The microchannel (10) is then completely buried in the substrate (2) by growing a microcrystalline structure to enclose the small surface port.

Abstract: A method for manufacturing a semiconductor substrate of a first concentration type is described, which comprises at least a buried insulating cavity, comprising the following steps:

Abstract: A process is presented for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2). The process forms in the substrate (2) at least one trench (4). A microchannel (10) is obtained starting from a small surface port of the trench (4) by anisotropic etching of the trench. The microchannel (10) is then completely buried in the substrate (2) by growing a microcrystalline structure to enclose the small surface port.

Abstract: A method for forming an interface free layer of silicon on a substrate of monocrystalline silicon is provided. According to the method, a substrate of monocrystalline silicon having a surface substantially free of oxide is provided. A silicon layer in-situ doped is deposited on the surface of the substrate in an oxygen-free environment and at a temperature below 700° C. so as to produce a monocrystalline portion of the silicon layer adjacent to the substrate and a polycrystalline portion of the silicon layer spaced apart from the substrate. The silicon layer is heated so as to grow the monocrystalline portion of the silicon layer through a part of the polycrystalline portion of the silicon layer. Also provided is a method for manufacturing a bipolar transistor.

Abstract: A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the reactor and evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally between 500 and 1200° C. and at a vacuum generally between 0.1 Pa and 60000 Pa. The treatment is performed at a time generally between 0.1 and 120 minutes, to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux. After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally between 700 and 1000° C. with nitrogen protoxide (N2O) for a time generally between 0.

Abstract: A method for forming an interface free layer of silicon on a substrate of monocrystalline silicon is provided. According to the method, a substrate of monocrystalline silicon having a surface substantially free of oxide is provided. A silicon layer in-situ doped is deposited on the surface of the substrate in an oxygen-free environment and at a temperature below 700° C. so as to produce a monocrystalline portion of the silicon layer adjacent to the substrate and a polycrystalline portion of the silicon layer spaced apart from the substrate. The silicon layer is heated so as to grow the monocrystalline portion of the silicon layer through a part of the polycrystalline portion of the silicon layer. Also provided is a method for manufacturing a bipolar transistor.