Abstract: A method of operating a semiconductor device having a plurality of memory cells programmable to a plurality of program states, wherein each of the program states is associated with a range of read currents bounded by a pair of reference read currents, comprising storing data by programming a first memory cell of the plurality of memory cells to a first program state of the plurality of program states, and programming a second memory cell of the plurality of memory cells to a second program state of the plurality of program states; and reading the data by reading the first memory cell to determine a first read current through the first memory cell, reading the second memory cell to determine a second read current through the second memory cell, and comparing the first read current, the second read current and a first one of the reference read currents to each other.

Abstract: In one example, a method comprises storing (n-1) partitions of a first image of code in a first set of banks in single-level cell format, wherein the first set of banks comprise (n-1) of n banks of flash memory cells; and storing (n-1) partitions of the first image and (n-1) partitions of a second image of code in a second set of banks in multi-level cell format, wherein the second set of banks comprise (n-1) of the n banks and the second set of banks comprises a bank not contained in the first set of banks.

Abstract: A programming method for a semiconductor device that includes programming a first memory cell to a first program state that is associated with a first program verify voltage and a first reference voltage such that the first memory cell has a first threshold voltage that meets or exceeds the first program verify voltage. The first program verify voltage is greater than the first reference voltage. A first read operation is performed which determines the first threshold voltage of the first memory cell has drifted down to between the first program verify voltage and the first reference voltage. In response to this determination, the first memory cell is programmed to increase the first threshold voltage of the first memory cell to meet or exceed the first program verify voltage.

Abstract: A semiconductor device includes an interface between first and second chiplets that comprises data lines and a redundant data line. The first and second chiplets include input/output modules each electrically coupled to one of the data lines. Each input/output module of the first chiplet is configured to send data over its corresponding data line to the corresponding input/output module of the second chiplet. In the case of a faulty data line, the corresponding one input/output module can reroute its data to a second input/output module for transmission over its data line, and the second input/output module can reroute its data to a third input/output module for transmission over its data line, and so on, until the last input/output module can reroute its data to the redundant data line for transmission over the redundant data line.

Abstract: A semiconductor device comprising a first die and a second die. The first die comprises a first substrate, non-planar MOSFET devices formed on the first substrate, and first contact pads electrically connected to the non-planar MOSFET devices. The second die comprises a second substrate, planar MOSFET devices formed on the second substrate, and second contact pads electrically connected to the planar MOSFET devices. Insulation material is formed on the first and second substrates. Contacts are formed on the insulation material. Paths of conductive material extend through the insulation material, and electrically connect to respective ones of the contacts, the first contact pads and the second contact pads.

Abstract: A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.

Abstract: A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.

Abstract: Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.

Abstract: Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.

Abstract: Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.

Abstract: Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.

Abstract: Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path.

Abstract: Disclosed herein is a device that includes a plurality of first word lines each extending from an associated one of the first terminals in a second direction toward to the second terminals and terminating between the first and second terminals, the second direction being substantially perpendicular to the first direction, and a plurality of second word lines each extending from an associated one of the second terminals in a third direction toward to the first terminals and terminating near to an end of an associated one of the first word lines, the third direction being opposite to the second direction, each of the second word lines being substantially aligned with an associated one of the first word lines.

Abstract: Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.

Abstract: A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad.

Abstract: Disclosed herein is a device that includes a plurality of first word lines each extending from an associated one of the first terminals in a second direction toward to the second terminals and terminating between the first and second terminals, the second direction being substantially perpendicular to the first direction, and a plurality of second word lines each extending from an associated one of the second terminals in a third direction toward to the first terminals and terminating near to an end of an associated one of the first word lines, the third direction being opposite to the second direction, each of the second word lines being substantially aligned with an associated one of the first word lines.

Abstract: Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.

Abstract: Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path.

Abstract: A sense amplifier includes a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.

Abstract: A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.