Abstract: A plurality of first storage elements store data. A plurality of second storage elements store an error correcting code based on a data sub-string of the data. A syndrome is generated based on the first and second storage elements. An erroneously programmed content of the first storage elements is corrected based on the syndrome.

Abstract: A reset generator for resetting at least one register in a register bank. The register generator comprises a scan mode input terminal configured to input a scan mode signal, a system reset input terminal configured to input a system reset signal, a secure reset output terminal configured to output a secure reset signal and a combination logic unit configured to combine the scan mode signal and the system reset signal. The combination is such that when the scan mode of the at least one register is activated, the secure reset signal is immediately activated for resetting the at least one register. The activation of the secure reset signal is independent of the system reset signal. The secure reset signal is deactivated when the system reset signal is deactivated and the secure reset signal follows the activation/deactivation cycles of the system reset signal after deactivation.

Abstract: A reset generator for resetting at least one register in a register bank. The register generator comprises a scan mode input terminal configured to input a scan mode signal, a system reset input terminal configured to input a system reset signal, a secure reset output terminal configured to output a secure reset signal and a combination logic unit configured to combine the scan mode signal and the system reset signal. The combination is such that when the scan mode of the at least one register is activated, the secure reset signal is immediately activated for resetting the at least one register. The activation of the secure reset signal is independent of the system reset signal. The secure reset signal is deactivated when the system reset signal is deactivated and the secure reset signal follows the activation/deactivation cycles of the system reset signal after deactivation.

Abstract: A plurality of first storage elements store data. A plurality of second storage elements store an error correcting code based on a data sub-string of the data. A syndrome is generated based on the first and second storage elements. An erroneously programmed content of the first storage elements is corrected based on the syndrome.

Abstract: System for testing a group of functionally independent memories (102) and for replacing failing memory words of the group of functionally independent memories (102) by redundant memory words, comprising: redundancy means 108) including at least one array of redundant memory words (108a) and address registers (108b) connected to at least one array of redundant memory words (108a); a test means (114); a group of first multiplexers (110) following the test means (114) and preceding the memories (102) and the at least one array of redundant memory words (108a); and a group of second multiplexers (112) following the memories (102) and the at least one array of redundant memory words (108a), wherein each second multiplexer (112) is connectable to the test means (114).

Abstract: An apparatus for determining the access time and the minimally allowable cycle time of a memory, comprising a clock for generating a signal which stimulates memory data output, programmable delay means for generating a delayed signal, sample-and-hold means for sampling the data output of the memory in response to the delayed signal, a comparator for comparing the sampled data to reference values, and a test status generator, wherein the test status depends on the results of more than one of the comparisons.

Abstract: System for testing a group of functionally independent memories and for replacing failing memory words