Patents by Inventor Simone Cassette

Simone Cassette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6858509
    Abstract: A collector-up heterojunction bipolar transistor including, stacked on a substrate, an emitter layer, a base layer, and a collector layer. In this transistor the surface area of the base-emitter junction is of smaller dimensions than the surface area of the base-collector junction. Further, the material of the base layer exhibits a sensitivity of the electrical conductivity to ion implantation that is lower than the sensitivity of the electrical conductivity of the material of the emitter layer to the same ion implantation.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: February 22, 2005
    Assignee: Thales
    Inventors: Sylvain Delage, Simone Cassette, Didier Floriot, Arnaud Girardot
  • Patent number: 6559534
    Abstract: A thermal capacitor component which includes, on a substrate, a stack of different layers defined in the form of a mesa terminating at its upper part in an electrical contact layer, which layer is coated with an electrically and thermally conducting layer surmounted by a heat sink element in contact with the conducting layer. The heat sink element has a plane shape. In addition, the component has at least one pad including another stack of layers which is also coated with an electrically and thermally conducting layer. The heat sink element is also in contact with the conducting layer of this stack so as to conduct the heat from the heat sink element into the substrate. Such a thermal capacitor may find application in the cooling of semiconductor components.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: May 6, 2003
    Assignee: Thomson-CSF
    Inventors: Didier Floriot, Sylvain DeLage, Simone Cassette, Jean-Pascal Duchemin
  • Publication number: 20020190273
    Abstract: The invention concerns a bipolar transistor with upper heterojunction comprising in particular stacked on a substrate: an emitter layer (EM); a base layer (BA), a collector layer (CO). In said transistor, the base-emitter junction surface is of smaller dimension than the base-collector junction surface and the material of the base layer has a lower electric conducting sensitivity to ion implantation than the electric conducting sensitivity of the material of the emitter layer to the same ion implant.
    Type: Application
    Filed: June 24, 2002
    Publication date: December 19, 2002
    Inventors: Sylvain Delage, Simone Cassette, Didier Floriot, Arnaud Girardot
  • Patent number: 6451659
    Abstract: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: September 17, 2002
    Assignee: Thomson-CSF
    Inventors: Sylvain Delage, Simone Cassette, Achim Henkel, Patrice Salzenstein
  • Publication number: 20020031892
    Abstract: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.
    Type: Application
    Filed: December 3, 1999
    Publication date: March 14, 2002
    Inventors: SYLVAIN DELAGE, SIMONE CASSETTE, ACHIM HENKEL, PATRICE SALZENSTEIN
  • Patent number: 6031255
    Abstract: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: February 29, 2000
    Assignee: Thomson-CSF
    Inventors: Sylvain Delage, Simone Cassette, Achim Henkel, Patrice Salzenstein
  • Patent number: 5719433
    Abstract: A semiconductor component that could be a power transistor type of component comprises mesa-structured elementary bipolar transistors. This component has a thick, metal heat sink of which a part (PI) takes the form of a bridge and a part is in contact with the substrate. The legs of the bridge lie on the entire unit constituted by the mesas. The heat sink made on the front face of the substrate may be connected to the rear face of the substrate comprising a ground plate. The discharging of the heat is thus appreciably fostered.
    Type: Grant
    Filed: July 25, 1996
    Date of Patent: February 17, 1998
    Assignee: Thomson-CSF
    Inventors: Sylvain Delage, Simone Cassette, Herve Blanck, Eric Chartier
  • Patent number: 5411632
    Abstract: Disclosed is a method for the etching of at least two layers of semiconductor materials having different natures, with a view to making a mesa for the self-alignment of the metallizations of a transistor. The heterojunction must comprise a first layer of a material containing As, which is etched by reactive ion etching, and a second layer of a material containing P which is etched chemically. Application to the making of HBT type vertical heterojunction transistors.
    Type: Grant
    Filed: November 5, 1993
    Date of Patent: May 2, 1995
    Assignee: Thomson-CSF
    Inventors: Sylvain Delage, Herve Blanck, Simone Cassette