Abstract: An electronic device may include wireless circuitry with processor circuitry, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as low noise amplifier circuitry for amplifying received radio-frequency signals. The amplifier circuitry may include an amplifier having an input and an output, an adjustable load component coupled to the input, and an adjustable feedback component coupled across the input and output. A control circuit may simultaneously adjust the load and feedback components to tune the gain of the amplifier circuitry while maintaining the input resistance at a desired target level. The load and feedback components can be the same or different types of adjustable passive components.

Abstract: An electronic device may include wireless circuitry with processor circuitry, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as low noise amplifier circuitry for amplifying received radio-frequency signals. The amplifier circuitry may include an amplifier having an input and an output, an adjustable load component coupled to the input, and an adjustable feedback component coupled across the input and output. A control circuit may simultaneously adjust the load and feedback components to tune the gain of the amplifier circuitry while maintaining the input resistance at a desired target level. The load and feedback components can be the same or different types of adjustable passive components.

Abstract: A computer system may periodically calibrate an oscillator subsystem, which includes a voltage-controlled oscillator circuit configured to generate an oscillator signal using code signal. In response to activation of a calibration mode, an iterative calibration operation may be performed on the voltage-controlled oscillator circuit. In some cases, performing a given iteration of the calibration operation includes determining a value of the code signal using a number of pulses in the oscillator signal sampled during a particular time period, along with previous values of the code signal and a slope of an error function associated with the difference between a desired frequency and a current frequency of the oscillator signal. In other cases, iterations may employ variable sampling times with error handling, in order to decrease the duration of the calibration operation while maintaining a target accuracy.

Abstract: A computer system may periodically calibrate an oscillator subsystem, which includes a voltage-controlled oscillator circuit configured to generate an oscillator signal using code signal. In response to activation of a calibration mode, an iterative calibration operation may be performed on the voltage-controlled oscillator circuit. In some cases, performing a given iteration of the calibration operation includes determining a value of the code signal using a number of pulses in the oscillator signal sampled during a particular time period, along with previous values of the code signal and a slope of an error function associated with the difference between a desired frequency and a current frequency of the oscillator signal. In other cases, iterations may employ variable sampling times with error handling, in order to decrease the duration of the calibration operation while maintaining a target accuracy.

Abstract: A sensor circuit included in a computer system may include multiple antennas, a control circuit, a mixer circuit, a transmitter circuit and a filter circuit. The control circuit may generate a baseband signal, which the mixer circuit may modulate using a modulation signal to generate a transmit signal. The transmitter circuit may transmit the transmit signal using a first antenna. The filter circuit may be configured to track a carrier frequency of the transmit signal and filter a reflected version of the transmit signal to generate an output signal.

Abstract: A frequency synthesizer circuit included in a sensor circuit of a computer system may include a voltage-controlled oscillator circuit that may generate an oscillator signal. A three-point injection technique may be used to modulate the frequency of the oscillator signal. The three-point injection includes a low-frequency component that drives a feedback divider, and two high-frequency components that drive the voltage-controlled oscillator circuit. The strengths of the three injection points are aligned using samples of a tune signal generated using results of a comparison of a referenced signal and a frequency divided version of the oscillator signal.

Abstract: A sensor circuit included in a computer system may include multiple antennas, a control circuit, a mixer circuit, a transmitter circuit and a filter circuit. The control circuit may generate a baseband signal, which the mixer circuit may modulate using a modulation signal to generate a transmit signal. The transmitter circuit may transmit the transmit signal using a first antenna. The filter circuit may be configured to track a carrier frequency of the transmit signal and filter a reflected version of the transmit signal to generate an output signal.

Abstract: A non-integer divider for dividing the frequency of a signal is disclosed. A non-integer divider includes a first divider that divides the frequency of a first signal. A mixer is coupled to receive the first signal, and a second signal having a frequency equivalent to that output by the first divider. The mixer outputs a third signal having a frequency based on respective frequencies of the first and second signal. A second divider receives and frequency divides the third signal to produce a fourth signal. A ratio of the frequency of the first signal to the fourth signal is a non-integer value.

Abstract: Various embodiments of a segmented R-DAC are disclosed. In one embodiment, a segmented R-DAC includes first and second DACs arranged to receive most and least significant bits, respectively. The segmented R-DAC also includes a first capacitor coupled between an output of the first DAC and an output of the second DAC, and a second capacitor coupled between the output of the second DAC and a ground node. The capacitance of the second capacitor has a value that is a predetermined multiple of the capacitance value of the first capacitor.

Abstract: A sensor circuit included in a computer system may include multiple antennas, a control circuit, a mixer circuit, a transmitter circuit and a filter circuit. The control circuit may generate a baseband signal, which the mixer circuit may modulate using a modulation signal to generate a transmit signal. The transmitter circuit may transmit the transmit signal using a first antenna. The filter circuit may be configured to track a carrier frequency of the transmit signal and filter a reflected version of the transmit signal to generate an output signal.

Abstract: A method and apparatus for measuring phase response in a radio receiver is disclosed. A radio receiver includes a digital-to-analog (D/A) conversion unit coupled to receive a test signal. The D/A conversion unit includes a number of single-bit digital-to-analog conversion (DAC) circuits coupled to receive the test signal and configured to convert it into the analog domain. Clock signals received by each of the single-bit DAC circuits are out of phase with respect to one another. The output of the D/A conversion unit is an analog signal that is a composite of the signals output by the DAC circuits therein. The analog signal is then conveyed to an analog-to-digital converter (ADC) and converted into an N-bit digital signal. The N-bit digital signal is then conveyed to a correlator to determine a phase response of the radio receiver.

Abstract: A non-integer divider for dividing the frequency of a signal is disclosed. A non-integer divider includes a first divider that divides the frequency of a first signal. A mixer is coupled to receive the first signal, and a second signal having a frequency equivalent to that output by the first divider. The mixer outputs a third signal having a frequency based on respective frequencies of the first and second signal. A second divider receives and frequency divides the third signal to produce a fourth signal. A ratio of the frequency of the first signal to the fourth signal is a non-integer value.

Abstract: An Nth-order loop filter includes N integrators (where N is an integer value). The loop filter includes an initialization path coupled between an input to the loop filter and an input of at least one of the integrators. A control circuit is coupled to the Nth order filter. During a reset phase, the control circuit causes an initialization voltage to be sampled into a capacitance of the initialization path. During an initialization phase immediately following the reset phase, the control circuit causes the initialization voltage to be conveyed to the input(s) of the at least one integrator.

Abstract: A minimally invasive, wireless ECoG microsystem is provided for chronic and stable neural recording. Wireless powering and readout are combined with a dual rectification power management circuitry to simultaneously power to and transmit a continuous stream of data from an implant with a micro ECoG array and an external reader. Area and power reduction techniques in the baseband and wireless subsystem result in over 10×IC area reduction with a simultaneous 3× improvement in power efficiency, enabling a minimally invasive platform for 64-channel recording. The low power consumption of the IC, together with the antenna integration strategy, enables remote powering at 3× below established safety limits, while the small size and flexibility of the implant minimizes the foreign body response.

Abstract: A continuous time sigma delta analog to digital converter may use a finite impulse response filter for delay compensation. In some embodiments, the filter may be simplified by using only the first and/or second filter coefficients.

Abstract: A continuous time sigma delta analog to digital converter may use a finite impulse response filter for delay compensation. In some embodiments, the filter may be simplified by using only the first and/or second filter coefficients.