Patents by Inventor Simone Lavizzari
Simone Lavizzari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11443174Abstract: A neural network circuit for providing a threshold weighted sum of input signals comprises at least two arrays of transistors with programmable threshold voltage, each transistor storing a synaptic weight as a threshold voltage and having a control electrode for receiving an activation input signal. Additionally, for each array of transistors, a reference network associated therewith, which provides a reference signal to be combined with the positive or negative weight current components of the transistors of the associated array, the reference signal having opposite sign compared to the weight current components of the associated array, thereby providing the threshold of the weighted sums of the currents. Further, at least one bitline is configured to receive the combined positive and/or negative current components, each combined with their associated reference signals.Type: GrantFiled: November 13, 2019Date of Patent: September 13, 2022Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU Leuven R&DInventors: Daniele Garbin, Simone Lavizzari
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Publication number: 20200151550Abstract: A neural network circuit for providing a threshold weighted sum of input signals comprises at least two arrays of transistors with programmable threshold voltage, each transistor storing a synaptic weight as a threshold voltage and having a control electrode for receiving an activation input signal. Additionally, for each array of transistors, a reference network associated therewith, which provides a reference signal to be combined with the positive or negative weight current components of the transistors of the associated array, the reference signal having opposite sign compared to the weight current components of the associated array, thereby providing the threshold of the weighted sums of the currents. Further, at least one bitline is configured to receive the combined positive and/or negative current components, each combined with their associated reference signals.Type: ApplicationFiled: November 13, 2019Publication date: May 14, 2020Inventors: Daniele Garbin, Simone Lavizzari
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Patent number: 9570677Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.Type: GrantFiled: February 21, 2016Date of Patent: February 14, 2017Assignee: Micron Technology, Inc.Inventors: Andrea Redaelli, Ugo Russo, Agostino Pirovano, Simone Lavizzari
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Publication number: 20160172587Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.Type: ApplicationFiled: February 21, 2016Publication date: June 16, 2016Inventors: Andrea Redaelli, Ugo Russo, Agostino Pirovano, Simone Lavizzari
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Patent number: 9299930Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.Type: GrantFiled: March 25, 2014Date of Patent: March 29, 2016Assignee: Micron Technology, Inc.Inventors: Andrea Redaelli, Ugo Russo, Agostino Pirovano, Simone Lavizzari
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Publication number: 20140206171Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.Type: ApplicationFiled: March 25, 2014Publication date: July 24, 2014Applicant: Micron Technology, Inc.Inventors: Andrea Redaelli, Ugo Russo, Agostino Pirovano, Simone Lavizzari
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Patent number: 8723155Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.Type: GrantFiled: November 17, 2011Date of Patent: May 13, 2014Assignee: Micron Technology, Inc.Inventors: Andrea Redaelli, Ugo Russo, Agostino Pirovano, Simone Lavizzari
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Publication number: 20130126812Abstract: Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.Type: ApplicationFiled: November 17, 2011Publication date: May 23, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Andrea Redaelli, Ugo Russo, Agostino Pirovano, Simone Lavizzari