Abstract: A power stage includes parallel FETs including a reference FET. An input PWM signal has a switching period. A current sensor senses current flowing through the power stage during switch-on period. A first circuit generates a first PWM signal having a duty-cycle indicative of reference FET driving losses for a reference current. A second circuit generates a second PWM signal having a duty-cycle indicative of reference FET conduction losses for that reference current. The duty cycles of the first and second PWM signals are compared to generate a comparison signal. The reference current is changed until a logic state of the comparison signal changes. A respective enable signal for each FET is generated by comparing the reference current to the sensed current flowing through the power stage. A FET driver circuit generates a respective drive signal for each FET by combining the respective enable signal with the input PWM signal.

Abstract: A half-bridge driver circuit periodically repeats switching cycles by closing a first FET via a first drive signal, detecting an instant when a current flowing through the first FET reaches a threshold and then opening the first FET and closing a second FET via a second drive signal. An error amplifier generates a control voltage by comparing a feedback signal with a reference signal, and a variable current generator generates a first current as a function of the control voltage. The error amplifier includes a proportional-integral controller, and a slope compensation circuit that generates a second current as a ramp signal. The threshold is generated by subtracting the second current from the first current. In response to detecting the instant, the second current is sampled and a signal indicative of the threshold is generated by subtracting the sampled second current from the first current.

Abstract: A power stage includes parallel FETs including a reference FET. An input PWM signal has a switching period. A current sensor senses current flowing through the power stage during switch-on period. A first circuit generates a first PWM signal having a duty-cycle indicative of reference FET driving losses for a reference current. A second circuit generates a second PWM signal having a duty-cycle indicative of reference FET conduction losses for that reference current. The duty cycles of the first and second PWM signals are compared to generate a comparison signal. The reference current is changed until a logic state of the comparison signal changes. A respective enable signal for each FET is generated by comparing the reference current to the sensed current flowing through the power stage. A FET driver circuit generates a respective drive signal for each FET by combining the respective enable signal with the input PWM signal.