Abstract: A method of entering combinatorial data on a data entry device (DED) including sensitive means which can be activated by an intermediary of at least one actuator allowing, according to a combination of sensitive means activated, an ad hoc computer program to designate and activate an object contained in a active correspondence table in memory, where the sensitive means are made up by at least three main detection zones Zi each made up of Fi (Fi=1, 2, 3 . . . ) distinct sensitive zones, comprising at least one step of designating/selecting an object from an active table; and a subsequent step of validation and production of the designated object, wherein for at least a first part of objects from the active table, the step of designation/selection of a single object can be achieved by designation of the object in successive combinatorial mode or by designation of the object in simultaneous combinatorial mode.

Abstract: A circuit for generating a cyclic prefix of a symbol comprised of a sequence of time samples, the prefix being the reproduction of the last samples of the symbol at the beginning of the symbol, the symbol being obtained by inverse Fourier transform of complex coefficients corresponding to respective frequencies. The circuit includes a multiplier that shifts the phase of each complex coefficient by a value proportional to its frequency, a memory for storing the samples at the beginning of the symbol, and a multiplexer that copies at the end of the symbol the stored samples.

Abstract: A method of entering combinatorial data on a data entry device (DED) including sensitive means which can be activated by an intermediary of at least one actuator allowing, according to a combination of sensitive means activated, an ad hoc computer program to designate and activate an object contained in a active correspondence table in memory, where the sensitive means are made up by at least three main detection zones Zi each made up of Fi (Fi=1, 2, 3 . . . ) distinct sensitive zones, comprising at least one step of designating/selecting an object from an active table; and a subsequent step of validation and production of the designated object, wherein for at least a first part of objects from the active table, the step of designation/selection of a single object can be achieved by designation of the object in successive combinatorial mode or by designation of the object in simultaneous combinatorial mode.

Abstract: A device for sending/receiving digital data is capable of processing different bit rates from a group of predetermined bit rates. The device may include a channel coding/decoding stage including an interleaver, a deinterleaver, and a memory whose minimum size is fixed as a function of the maximum bit rate of the group of predetermined bit rates. The memory may have a first memory space assigned to the interleaver and a second memory space assigned to the deinterleaver. The size of each of the two memory spaces may be set as a function of the bit rate actually processed by the device.

Abstract: A circuit for generating a cyclic prefix of a symbol comprised of a sequence of time samples, the prefix being the reproduction of the last samples of the symbol at the beginning of the symbol, the symbol being obtained by inverse Fourier transform of complex coefficients corresponding to respective frequencies. The circuit includes a multiplier that shifts the phase of each complex coefficient by a value proportional to its frequency, a memory for storing the samples at the beginning of the symbol, and a multiplexer that copies at the end of the symbol the stored samples.

Abstract: Interleaved type processing includes a preprocessing phase in which for each initial symbol received an auxiliary symbol that includes N auxiliary complex samples is formulated, and a processing phase that includes for each auxiliary symbol an inverse Fourier transform calculation of size N. The processing phase includes elementary processing of the butterfly type corresponding to several stages of a general butterfly-like calculation graph. The various stages of the graph are implemented within a pipelined architecture. Upon receiving an initial symbol, two separate random access memories are simultaneously used to respectively store in a first memory the auxiliary symbol corresponding to this initial symbol, and to perform on the basis of the content of the second memory the elementary processing corresponding to a first stage of the graph. The two memories are swapped with each new receipt of an initial symbol.

Abstract: A device includes a processor able to calculate the direct or inverse Fourier transform of the product of a complex input symbol of size N times a complex sinusoidal waveform of period n. The calculation is performed on the basis of elementary processes of the butterfly type corresponding to several stages of a general butterfly-shaped calculation graph where n is an integer less than N. The processor includes a first elementary processor able to simultaneously perform the multiplication and the Fourier transform calculations relating to the first stage of the graph.

Abstract: The device for sending/receiving digital data is capable of processing different bit rates from a group of predetermined bit rates. It includes a channel coding/decoding stage including interleaving means MET and deinterleaving means MDET including a memory MM whose minimum size is fixed as a function of the maximum bit rate of said group and having a first memory space ESM1 assigned to the interleaving means and a second memory space ESM2 assigned to the deinterleaving means. The size of each of the two memory spaces is parameterable as a function of the bit rate actually processed by the device.