Abstract: Disclosed herein is a redundancy resource comparator for a bus architecture of a memory device for comparing an address signal being received from an address signal bus and a redundancy address being stored in a latch of the memory device. Disclosed is also a corresponding bus architecture and comparison method.

Abstract: Disclosed herein is a redundancy resource comparator for a bus architecture of a memory device for comparing an address signal being received from an address signal bus and a redundancy address being stored in a latch of the memory device. Disclosed is also a corresponding bus architecture and comparison method.

Abstract: A decoder structure for selecting a column of memory cells in a memory architecture includes an array of decoder cells organized into different rows. Each row includes a plurality of sub-column groups of decoder cells configured to receive a same input signal. Each sub-column group of decoder cells of a row is coupled to a sub-column group of decoder cells of a subsequent row. The decoder structure further includes a plurality of precharge transistors connected to the decoder cells of a row so as to form a plurality of inverter blocks.

Abstract: A decoder structure for selecting a column of memory cells in a memory architecture includes an array of decoder cells organized into different rows. Each row includes a plurality of sub-column groups of decoder cells configured to receive a same input signal. Each sub-column group of decoder cells of a row is coupled to a sub-column group of decoder cells of a subsequent row. The decoder structure further includes a plurality of precharge transistors connected to the decoder cells of a row so as to form a plurality of inverter blocks.

Abstract: Disclosed herein is a bus architecture for transferring data from a bus signal generator to a receiver comprises a plurality of bus lines comprising a plurality of odd bus lines and a plurality of even bus lines, each of the even bus lines being arranged between adjacent odd bus lines; and at least one repeater coupled with the plurality of bus lines, wherein each of the plurality of bus lines comprises a plurality of unit length paths(ULPs), wherein the repeater is arranged between adjacent ULPs of the bus lines, wherein one of the adjacent ULPs is coupled to one among inputs of the repeater and the other of the adjacent ULPs is coupled to one among outputs of the repeater for each of the bus lines, wherein either of the odd bus lines or the even bus lines are inverting bus lines.