Abstract: Live objects in heap memory exceeding a threshold size and that have not been recently accessed are compressed or offloaded to secondary memory or storage. Compressing or offloading an object can further be based on how old the object is, which can be determined based on how many garbage collections the object has survived. Objects comprising references to other objects can be split into two sub-objects, one containing value fields that is compressed or offloaded and one containing reference fields that remains uncompressed in heap memory. Heap memory can undergo compaction after objects are compressed or offloaded. Compression accelerators can be used for compression and the decision of whether to compress or offload an object can be based on accelerator throughput, latency, availability, as well as other computing system metrics or characteristics. The compressing and offloading of objects and subsequent compaction can make more heap memory available for object allocation.

Abstract: Methods, apparatus, systems, and articles of manufacture to facilitate field-programmable gate array support during runtime execution of computer readable instructions are disclosed herein. An example apparatus includes a compiler to, prior to runtime, compile a block of code written as high level source code into a first hardware bitstream kernel and a second hardware bitstream kernel; a kernel selector to select the first hardware bitstream kernel based on an attribute to be dispatched during runtime; a dispatcher to dispatch the first hardware bitstream kernel to a field programmable gate array (FPGA) during runtime; and the kernel selector to, when an FPGA attribute does not satisfy a threshold during runtime, adjust the selection of the first hardware bitstream kernel to the second hardware bitstream kernel to be dispatched during runtime.

Abstract: Methods, apparatus, systems, and articles of manufacture to facilitate field-programmable gate array support during runtime execution of computer readable instructions are disclosed herein. An example apparatus includes a compiler to, prior to runtime, compile a block of code written as high level source code into a first hardware bitstream kernel and a second hardware bitstream kernel; a kernel selector to select the first hardware bitstream kernel based on an attribute to be dispatched during runtime; a dispatcher to dispatch the first hardware bitstream kernel to a field programmable gate array (FPGA) during runtime; and the kernel selector to, when an FPGA attribute does not satisfy a threshold during runtime, adjust the selection of the first hardware bitstream kernel to the second hardware bitstream kernel to be dispatched during runtime.

Abstract: A microprocessor with an execution stage (26) including a plurality of execution units and an instruction memory (32) for storing instructions. The microprocessor further includes circuitry for retrieving (14) instructions from the instruction memory. This retrieving circuitry may retrieve one instruction simultaneously with the execution of another instruction by one of the plurality of execution units. Further, this retrieving circuitry includes a branch target memory (30) for storing a plurality of information fields (30r) corresponding to a branch instruction. The information fields include at least a target instruction address (Tn), a prediction field (Pn) indicating whether or not program flow should pass to the target instruction address, and an accuracy measure (PPAn) indicating accuracy for past prediction fields.

Abstract: A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of intermediary stages (40 through 52), and to an ending stage (54) of the plurality of successive instruction stages. The microprocessor also comprises a storage circuit (58) coupled to receive program thread information output from a first stage (48) of the intermediary stages. Still further, the microprocessor comprises selection circuitry (56) comprising a first input, a second input, and an output for outputting output information from its first and second inputs. The first input of the selection circuitry is coupled to receive output information output from the first stage. The second input of the selection circuitry is coupled to receive program thread information output from the storage circuit.