Abstract: According to an embodiment, a circuit includes a memory cell array storing memory words with data bits, data check bits, and address check bits. An error correction code (ECC) logic circuit includes an address ECC generator circuit generating address check bits, a data ECC generator circuit generating data check bits, an address ECC checker circuit verifying address check bits, and a data ECC checker/correction circuit verifying and correcting data bits using data check bits. A logic circuit arranges the bits within each memory word based on a predetermined arrangement. The address check bits may be scrambled within each word, with at least one as the least or most significant bit. The address ECC may use Single Error Detection Double Error Decoding (SEDDED) and the data ECC may use Single Error Correction Double Error Detection (SECDED). The architecture provides enhanced error detection and correction capabilities for high-integrity memory applications.

Abstract: A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.

Abstract: A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.