Abstract: The present invention provides an apparatus for measuring electrical impedance comprising: two input electrodes contacted to a subject for measuring impedance; a difference amplifier to which two signals inputted to the two input electrodes are inputted; a device for extracting a common mode component of two signals inputted to the two input electrodes; the third electrode contacted to the subject for measuring impedance; the first multiplier to which the common mode component is inputted; the first filter coupled with the first multiplier; the second multiplier coupled with the first filter; wherein a feedback signal outputted from the second multiplier is inputted to the third electrode.

Abstract: The present invention provides an apparatus for measuring electrical impedance comprising: two input electrodes contacted to a subject for measuring impedance; a difference amplifier to which two signals inputted to the two input electrodes are inputted; a device for extracting a common mode component of two signals inputted to the two input electrodes; the third electrode contacted to the subject for measuring impedance; the first multiplier to which the common mode component is inputted; the first filter coupled with lo the first multiplier; the second multiplier coupled with the first filter; wherein a feedback signal outputted from the second multiplier is inputted to the third electrode.

Abstract: A turbo encoding and decoding method and apparatus iteratively performs its decoding process as many times as the number of decoding times adaptively determined according to an amount of errors caused in a transmitted information bit stream so as to correct the errors, wherein the amount of errors is detected by checking a state of parity bits inserted into information bits during a turbo encoding process. The turbo encoder first inserts the parity bits into the information bits and encodes the parity bit inserted information bits to thereby produce the information bit stream to be transmitted.

Abstract: A process for formation of a large area flat panel display, and particularly a process for formation of a large area flat panel display using a side junction is disclosed, in which a large area is achieved by utilizing a side junction. More specifically, there is provided a process for formation of a thin film transistor liquid crystal display which can be used on all kinds of flat panel displays which uses glass as the substrate. The process for formation of a large area flat panel display utilizing a side junction according to the present invention includes the steps of: applying a side junction process on thin film transistor unit panels 2 so as to obtain a large area; and coupling a common electrode panel with said large area thin film transistor panel formed through said side junction process.

Abstract: A micro light valve which is corresponding to each of pixels for display and which passes or shuts a light beam by electrostatic force to display images, said light valve comprising a data electrode formed on a substrate and connected with each of data lines through a via; a selection electrode formed on the substrate and connected with each of selection lines; a common electrode formed between the selection and data electrodes; a flat-shaped micro shifting element capable of moving in linear direction and which serves as a resistance body; insulating layers formed respectively between the shifting element and each of the electrodes; a frame for serving as a black matrix, which has a guiding means for guiding the shifting element; and the three electrodes for receiving externally applied driving signals to drive the shifting element and which serve as stationary elements with three phases.

Abstract: A flat display device has a plurality of pixels and a plurality of micro light valves which correspond to each of the pixels thereof, and has a plurality of selection lines and data lines disposed in a matrix the micro light valves each comprise a data electrode to be connected with each of the data lines through a via, a selection electrode to be connected with each of the selection lines, a common electrode formed between the selection and data electrodes, a frame, and a shifting element capable of being moved in the frame by driving signals to be applied to the data and selection electrodes, so as to pass or shut off a light beam. A first driving means is connected to the respective selection lines, for supplying a predetermined selection signal for said light valves; and a second driving means is connected to the respective data lines, for supplying a predetermined data signal for said light valve.

Abstract: A method is disclosed for manufacturing a very fast micro light valve of the type used to control the passage of light through a pixel. The method comprises preparing a substrate, which can be made of glass, and forming transparent electrodes on the main surface of the substrate. Next an insulating layer is deposited on the substrate and a first sacrificial layer is formed on the insulating layer. A pattern shifting element layer is formed on the first sacrificial layer and a second sacrificial layer is formed on the substrate and provided with a shifting element layer. After portions of the sacrificial layers are removed by etching to form a frame contact portion, a patterned frame layer is formed on the frame contact portion. Then a frame and a shifting element capable of moving in the frame under an applied external electrostatic force are formed by removing the remaining sacrificial layers.

Abstract: There is disclosed a semiconductor device having a plurality of chips in which a predetermined extended addresses are allocated for each of the chips to select the chips in a multiple-chip module, the device comprising: a plurality of semiconductor chip selectors equipped in said semiconductor device, for supplying an internal chip select signals to select the chips in response to said extended addresses and a module select signal; and each of said semiconductor chip selectors having a plurality of decoders for receiving the extended addresses and outputting a predetermined logic signal, and an AND gate for receiving said module select signal and said logic signal of each of said decoders and outputting said internal chip select signals.