Patents by Inventor Sin-Deok Kang

Sin-Deok Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Calibrating resistance for integrated circuit
    Patent number: 8471590
    Abstract: An integrated circuit includes a first ODT unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line through which data is transferred, and adjust a resistance value. The input buffer is configured to drive input data by buffering the data in response to a level of a reference voltage, wherein the driving of the input data is adjusted in response to the pull-up code and the pull-down code.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: June 25, 2013
    Assignee: SK Hynix Inc.
    Inventor: Sin Deok Kang
  • CALIBRATING RESISTANCE FOR INTEGRATED CIRCUIT
    Publication number: 20120007632
    Abstract: An integrated circuit includes a first ODT unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line through which data is transferred, and adjust a resistance value. The input buffer is configured to drive input data by buffering the data in response to a level of a reference voltage, wherein the driving of the input data is adjusted in response to the pull-up code and the pull-down code.
    Type: Application
    Filed: June 14, 2011
    Publication date: January 12, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Sin Deok KANG
  • Semiconductor memory device with increased domain crossing margin
    Patent number: 7450442
    Abstract: A semiconductor memory device with an increased domain crossing margin is provided. The semiconductor memory device includes: a data input buffer for receiving an external data in response to a driving signal; a DQS input buffer for receiving an external data strobe signal in response to the driving signal; a delay unit for delaying an output signal of the DQS input buffer by a predetermined time; a division unit for dividing an output signal of the DQS input buffer to output a plurality of internal data strobe signals; and a data align unit for aligning an output data of the delay unit in response to the corresponding internal data strobe signals to output a plurality of align data.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: November 11, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sin-Deok Kang
  • Semiconductor memory device with increased domain crossing margin
    Publication number: 20070002644
    Abstract: A semiconductor memory device with an increased domain crossing margin is provided. The semiconductor memory device includes: a data input buffer for receiving an external data in response to a driving signal; a DQS input buffer for receiving an external data strobe signal in response to the driving signal; a delay unit for delaying an output signal of the DQS input buffer by a predetermined time; a division unit for dividing an output signal of the DQS input buffer to output a plurality of internal data strobe signals; and a data align unit for aligning an output data of the delay unit in response to the corresponding internal data strobe signals to output a plurality of align data.
    Type: Application
    Filed: December 29, 2005
    Publication date: January 4, 2007
    Inventor: Sin-Deok Kang