Patents by Inventor Sin-Ho Yang
Sin-Ho Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240083384Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.Type: ApplicationFiled: February 3, 2023Publication date: March 14, 2024Applicants: Hyundai Motor Company, Kia Corporation, Daechang Seat Co.,LTD-Dongtan, Hyundai Transys Inc.Inventors: Sang Soo LEE, Chan Ho JUNG, Mu Young KIM, Sang Hark LEE, Ho Suk JUNG, Deok Soo LIM, Sang Do PARK, In Sun BAEK, Sin Chan YANG, Chan Ki CHO, Myung Soo LEE, Jae Yong JANG, Jun Sik HWANG, Ho Sung KANG, Hae Dong KWAK, Hyun Tak KO
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Publication number: 20220164143Abstract: A memory device includes: a plurality of memory cells; soft read logic configured to generate soft data by reading data from the plurality of memory cells in response to a soft read command from a controller, the soft data including at least a major symbol and at least a minor symbol; a compressor configured to generate compressed data by: encoding, into a code alphabet having a second length, a major source alphabet including repetitions of the major symbol by a first length among a plurality of source alphabets included in the soft data, and encoding, into a code alphabet having a longer length than the second length, a minor source alphabet including repetitions of the major symbol by a shorter length than the first length and ending with one minor symbol; and an interface configured to provide the compressed data to the controller.Type: ApplicationFiled: May 19, 2021Publication date: May 26, 2022Inventors: Dae Sung KIM, Sung Ho AHN, Sin Ho YANG, Jae Hyeong JEONG
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Patent number: 9037950Abstract: A memory controller and an operating method of the memory controller are provided. The operating method includes: performing error correction on data, including a plurality of chunks, in a unit of a chunk; determining if a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in an error location polynomial for a last chunk among the plurality of chunks, is all zero; and controlling an output time of an error-corrected first chunk based on a result of the determining.Type: GrantFiled: December 26, 2012Date of Patent: May 19, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Phil Kong, Soong Mann Shin, Myung Suk Choi, Sin Ho Yang
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Patent number: 8938576Abstract: A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host.Type: GrantFiled: August 27, 2014Date of Patent: January 20, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-phil Jo, Chang-il Son, Kyu-hyun Shim, Sin-ho Yang
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Publication number: 20140365721Abstract: A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host.Type: ApplicationFiled: August 27, 2014Publication date: December 11, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Nam-phil Jo, Chang-il Son, Kyu-hyun Shim, Sin-ho Yang
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Patent number: 8856433Abstract: A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host.Type: GrantFiled: April 5, 2013Date of Patent: October 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-phil Jo, Chang-il Son, Kyu-hyun Shim, Sin-ho Yang
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Publication number: 20130268803Abstract: A memory controller and an operating method of the memory controller are provided. The operating method includes: performing error correction on data, including a plurality of chunks, in a unit of a chunk; determining if a coefficient of each term of which a degree is equal to or greater than a degree of a reference-degree term, in an error location polynomial for a last chunk among the plurality of chunks, is all zero; and controlling an output time of an error-corrected first chunk based on a result of the determining.Type: ApplicationFiled: December 26, 2012Publication date: October 10, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Phil KONG, Soong Mann SHIN, Myung Suk CHOI, Sin Ho YANG
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Publication number: 20130227205Abstract: A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host.Type: ApplicationFiled: April 5, 2013Publication date: August 29, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-phil Jo, Chang-il Son, Kyu-hyun Shim, Sin-ho Yang
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Patent number: 8423703Abstract: A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host.Type: GrantFiled: July 27, 2007Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Phil Jo, Chang-Il Son, Kyu-Hyun Shim, Sin-Ho Yang
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Patent number: 7698524Abstract: An apparatus for controlling data exchange with a memory device includes an interface configured to receive an arbitration signal indicating when the apparatus has use of a shared bus and an interface to the memory device configured to provide a clock signal to the memory device that synchronizes data exchange between the apparatus and the memory device. A selection circuit selectively supplies the clock signal to the memory device responsive to the arbitration signal.Type: GrantFiled: May 5, 2006Date of Patent: April 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Duck Lee, Sam-Yong Bahng, Sin-Ho Yang, Kui-Yon Mun
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Publication number: 20080034142Abstract: A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host.Type: ApplicationFiled: July 27, 2007Publication date: February 7, 2008Inventors: Nam-Phil Jo, Chang-Il Son, Kyu-Hyun Shim, Sin-Ho Yang
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Publication number: 20070124558Abstract: An apparatus for controlling data exchange with a memory device includes an interface configured to receive an arbitration signal indicating when the apparatus has use of a shared bus and an interface to the memory device configured to provide a clock signal to the memory device that synchronizes data exchange between the apparatus and the memory device.Type: ApplicationFiled: May 5, 2006Publication date: May 31, 2007Inventors: Chang-Duck Lee, Sam-Yong Bahng, Sin-Ho Yang, Kui-Yon Mun
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Publication number: 20060174148Abstract: Disclosed is a controller and method for regulating a power-down mode in a memory card system. The memory card controller includes a central processor unit, a direct memory accessing (DMA) unit, a buffer, and a power-down detector. The central processor unit accepts commands from a host and the DMA unit stores the number of blocks requested by the host in response to instructions of the central processor unit. The buffer stores data that are read from an external storage device through the DMA unit. The power-down detector outputs a control signal to regulate a system clock by means of detecting a storage condition of the buffer and a read-out condition of the host. As the power-down mode begins, if the host does not read data stored in the buffer even when the buffer is full with data, it is possible to reduce power consumption by the memory card controller.Type: ApplicationFiled: February 2, 2006Publication date: August 3, 2006Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sin-Ho Yang