Abstract: Provided are a vehicle sensor cleaning apparatus and a control method thereof. The vehicle sensor cleaning apparatus includes a liquid sprayer configured to spray washer fluid on at least one sensor arranged in a vehicle, an air sprayer configured to spray air on the at least one sensor, a liquid controller configured to control washer fluid spraying of the liquid sprayer, and an air controller configured to control air spraying of the air sprayer.

Abstract: A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period.

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract: A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.

Abstract: A semiconductor apparatus includes a plurality of stacked chips. At least two of the chips are configured to receive a column command and generate a column control signal based on the column command. Generation timing of the column control signal generated based on a column command in one of the at least two chips substantially coincide with the generation timing in the other of the at least two of the plurality of chips.

Abstract: A power supply control circuit includes a power supply control unit configured to receive a rank mode signal and generate a plurality of power supply enable signals based on a rank mode designated by the rank mode signal, a chip selection signals and bank address signals; and a plurality of power blocks configured to supply power to a plurality of memory banks of a plurality of chips based on the plurality of power supply enable signals.

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract: A semiconductor integrated circuit having a multi-chip structure includes a number of stacked semiconductor chips. Each of the semiconductor chips includes a first through electrode formed through the semiconductor chip, a first bump pad formed over the semiconductor chip at a region where the first bump pad is separated from the first through electrode, a first internal circuit formed inside the semiconductor chip, coupled to the first through electrode through a first metal path, and coupled to the first bump pad through a second metal path; and a redistribution layer (RDL) formed over a backside of the semiconductor chip.

Abstract: A semiconductor memory device includes a bit line sense amplification unit configured to sense/amplify data loaded on a bit line, and a driving control unit configured to supply a power line of the bit line sense amplification unit with an overdriving voltage in an overdriving period and supply an internal voltage line with a voltage of the power line of the bit line sense amplification unit in a discharge driving period.

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract: A semiconductor apparatus having a plurality of stacked chips includes: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate an chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal is configured to enable the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal.

Abstract: A semiconductor apparatus having a plurality of stacked chips includes: a through silicon via (TSV) configured to couple the plurality of chips together and configured to be coupled in series to a plurality of voltage drop units; a plurality of signal conversion units, each of which is configured to convert a voltage outputted from the voltage drop unit of the corresponding one of the plurality of chips to a digital code signal and provide the digital code signal as chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is configured to compare the chip identification signal with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips.

Abstract: A semiconductor apparatus includes a plurality of pump control units respectively located in a plurality of chips, connected in series through a first TSV, and configured to sequentially delay a period signal, transmit delayed period signals and generate pump control signals based on the period signal or the delayed period signals; and a plurality of voltage pump units respectively located in the plurality of chips, and configured to generate a pumping voltage in response to the pump control signals generated from the plurality of pump control units.

Abstract: A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.

Abstract: A semiconductor integrated circuit having a multi-chip structure includes a number of stacked semiconductor chips. Each of the semiconductor chips includes a first through electrode formed through the semiconductor chip, a first bump pad formed over the semiconductor chip at a region where the first bump pad is separated from the first through electrode, a first internal circuit formed inside the semiconductor chip, coupled to the first through electrode through a first metal path, and coupled to the first bump pad through a second metal path; and a redistribution layer (RDL) formed over a backside of the semiconductor chip.

Abstract: A power supply control circuit includes a power supply control unit configured to receive a rank mode signal and generate a plurality of power supply enable signals based on a rank mode designated by the rank mode signal, a chip selection signals and bank address signals; and a plurality of power blocks configured to supply power to a plurality of memory banks of a plurality of chips based on the plurality of power supply enable signals.

Abstract: A semiconductor apparatus includes a plurality of pump control units respectively located in a plurality of chips, connected in series through a first TSV, and configured to sequentially delay a period signal, transmit delayed period signals and generate pump control signals based on the period signal or the delayed period signals; and a plurality of voltage pump units respectively located in the plurality of chips, and configured to generate a pumping voltage in response to the pump control signals generated from the plurality of pump control units.

Abstract: A voltage trimming circuit of a semiconductor memory apparatus may include a first voltage generation block configured to select voltage levels of a first node and a second node and divide a voltage between the first node and the second node to generate a first division voltage group; a second voltage generation block configured to select voltage levels of a third node and a fourth node and divide a voltage between the third node and the fourth node to generate a second division voltage group; a first switch block configured to select one division voltage of the first division voltage group to output the selected division voltage as a first reference voltage; and a second switch block configured to select one division voltage of the second division voltage group to output the selected division voltage as a second reference voltage.